Luke Wren 91be98f2da Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)		2022-07-06 23:53:11 +01:00
..
riscv-tests@b6ac1971d1	Rebase riscv-tests against upstream, and pick up new semihosting file io test	2022-07-04 00:45:20 +01:00
debug.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
run-debug-tests.sh	Rebase riscv-tests against upstream, and pick up new semihosting file io test	2022-07-04 00:45:20 +01:00
run-isa-tests.sh	Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.	2022-05-28 17:22:28 +01:00
run-smp-debug-tests.sh	Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed	2022-07-03 23:34:12 +01:00