Luke Wren 719c21fec3 Add IRQ tests. Disable waves by default in runtests		2021-12-12 15:53:04 +00:00
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bitmanip-random	Fix sim cmdline in bitmanip-random tests	2021-12-11 13:13:21 +00:00
common	Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test	2021-12-12 14:58:50 +00:00
coremark	Fix remaining fallout from tb args change	2021-12-11 09:53:39 +00:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
embench	Fix remaining fallout from tb args change	2021-12-11 09:53:39 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
riscv-compliance	Remove padding after vector table in init.S	2021-12-11 12:22:23 +00:00
riscv-tests	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Correct mnemonic when logging unsigned sltiu instruction	2021-10-08 12:02:37 +01:00
sw_testcases	Add IRQ tests. Disable waves by default in runtests	2021-12-12 15:53:04 +00:00
tb_cxxrtl	Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test	2021-12-12 14:58:50 +00:00