334 lines
21 KiB
Verilog
334 lines
21 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module hazard3_decode #(
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire clk,
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input wire rst_n,
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input wire [31:0] fd_cir,
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input wire [1:0] fd_cir_err,
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input wire [1:0] fd_cir_vld,
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output wire [1:0] df_cir_use,
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output wire df_cir_lock,
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output wire [W_ADDR-1:0] d_pc,
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input wire debug_mode,
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input wire m_mode,
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input wire permit_wfi,
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output wire d_starved,
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input wire x_stall,
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input wire f_jump_now,
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input wire [W_ADDR-1:0] f_jump_target,
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input wire x_jump_not_except,
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output reg [W_DATA-1:0] d_imm,
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output reg [W_REGADDR-1:0] d_rs1,
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output reg [W_REGADDR-1:0] d_rs2,
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output reg [W_REGADDR-1:0] d_rd,
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output reg [W_ALUSRC-1:0] d_alusrc_a,
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output reg [W_ALUSRC-1:0] d_alusrc_b,
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output reg [W_ALUOP-1:0] d_aluop,
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output reg [W_MEMOP-1:0] d_memop,
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output reg [W_MULOP-1:0] d_mulop,
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output reg d_csr_ren,
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output reg d_csr_wen,
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output reg [1:0] d_csr_wtype,
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output reg d_csr_w_imm,
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output reg [W_BCOND-1:0] d_branchcond,
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output reg [W_ADDR-1:0] d_addr_offs,
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output reg d_addr_is_regoffs,
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output reg [W_EXCEPT-1:0] d_except,
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output reg d_wfi
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);
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`include "rv_opcodes.vh"
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`include "hazard3_ops.vh"
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localparam HAVE_CSR = CSR_M_MANDATORY || CSR_M_TRAP || CSR_COUNTER;
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// ----------------------------------------------------------------------------
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// Expand compressed instructions
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wire [31:0] d_instr;
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wire d_instr_is_32bit;
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wire d_invalid_16bit;
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reg d_invalid_32bit;
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wire d_invalid = d_invalid_16bit || d_invalid_32bit;
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hazard3_instr_decompress #(
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.PASSTHROUGH(!EXTENSION_C)
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) decomp (
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.instr_in (fd_cir),
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.instr_is_32bit (d_instr_is_32bit),
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.instr_out (d_instr),
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.invalid (d_invalid_16bit)
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);
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// Decode various immmediate formats
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wire [31:0] d_imm_i = {{21{d_instr[31]}}, d_instr[30:20]};
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wire [31:0] d_imm_s = {{21{d_instr[31]}}, d_instr[30:25], d_instr[11:7]};
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wire [31:0] d_imm_b = {{20{d_instr[31]}}, d_instr[7], d_instr[30:25], d_instr[11:8], 1'b0};
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wire [31:0] d_imm_u = {d_instr[31:12], {12{1'b0}}};
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wire [31:0] d_imm_j = {{12{d_instr[31]}}, d_instr[19:12], d_instr[20], d_instr[30:21], 1'b0};
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// ----------------------------------------------------------------------------
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// PC/CIR control
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// Must not flag bus error for a valid 16-bit instruction *followed by* an
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// error, because instruction fetch errors are speculative, and can be
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// flushed by e.g. a branch instruction. Note the 16 LSBs must be valid for
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// us to know an instruction's size.
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wire d_except_instr_bus_fault = fd_cir_vld > 2'd0 && fd_cir_err[0] ||
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fd_cir_vld > 2'd1 && d_instr_is_32bit && fd_cir_err[1];
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assign d_starved = ~|fd_cir_vld || fd_cir_vld[0] && d_instr_is_32bit;
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wire d_stall = x_stall || d_starved;
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assign df_cir_use =
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d_starved || d_stall ? 2'h0 :
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d_instr_is_32bit ? 2'h2 : 2'h1;
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// CIR Locking is required if we successfully assert a jump request, but decode is stalled.
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// (This only happens if decode stall is caused by X stall, not if fetch is starved!)
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// The reason for this is that, if the CIR is not locked in, it can be trashed by
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// incoming fetch data before the roadblock clears ahead of us, which will squash any other
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// side effects this instruction may have besides jumping! This includes:
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// - Linking for JAL
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// - Mispredict recovery for branches
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// Note that it is not possible to simply gate the jump request based on X stalling,
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// because X stall is a function of hready, and jump request feeds haddr htrans etc.
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wire jump_caused_by_d = f_jump_now && x_jump_not_except;
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wire assert_cir_lock = jump_caused_by_d && d_stall;
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wire deassert_cir_lock = !d_stall;
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reg cir_lock_prev;
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assign df_cir_lock = (cir_lock_prev && !deassert_cir_lock) || assert_cir_lock;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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cir_lock_prev <= 1'b0;
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else
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cir_lock_prev <= df_cir_lock;
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reg [W_ADDR-1:0] pc;
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wire [W_ADDR-1:0] pc_next = pc + (d_instr_is_32bit ? 32'h4 : 32'h2);
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assign d_pc = pc;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pc <= RESET_VECTOR;
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end else begin
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if ((f_jump_now && !assert_cir_lock) || (cir_lock_prev && deassert_cir_lock)) begin
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pc <= f_jump_target;
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`ifdef FORMAL
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// Being cheeky above to save a 32 bit mux. Check that we never get an M target by mistake.
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// FIXME disabled this for now -- we do sometimes see an exception taking
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// place during the stall, which then leads to a different branch target
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// appearing. (i.e. f_jump_now is asserted for two cycles, the first one
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// from this instruction and the second from the exception; this is ok,
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// because the exception will return to this branch when done.)
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// if (cir_lock_prev && deassert_cir_lock)
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// assert(f_jump_target == d_jump_target);
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`endif
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end else if (!d_stall && !df_cir_lock) begin
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pc <= pc_next;
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end
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end
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end
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always @ (*) begin
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casez ({|EXTENSION_A, |EXTENSION_ZIFENCEI, d_instr[6:2]})
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{1'bz, 1'bz, 5'b11011}: d_addr_offs = d_imm_j ; // JAL
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{1'bz, 1'bz, 5'b11000}: d_addr_offs = d_imm_b ; // Branches
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{1'bz, 1'bz, 5'b01000}: d_addr_offs = d_imm_s ; // Store
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{1'bz, 1'bz, 5'b11001}: d_addr_offs = d_imm_i ; // JALR
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{1'bz, 1'bz, 5'b00000}: d_addr_offs = d_imm_i ; // Loads
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{1'b1, 1'bz, 5'b01011}: d_addr_offs = 32'h0000_0000; // Atomics
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{1'bz, 1'b1, 5'b00011}: d_addr_offs = 32'h0000_0004; // Zifencei
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default: d_addr_offs = 32'hxxxx_xxxx;
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endcase
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end
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// ----------------------------------------------------------------------------
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// Decode X controls
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localparam X0 = {W_REGADDR{1'b0}};
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always @ (*) begin
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// Assign some defaults
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d_rs1 = d_instr[19:15];
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d_rs2 = d_instr[24:20];
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d_rd = d_instr[11: 7];
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d_imm = d_imm_i;
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d_alusrc_a = ALUSRCA_RS1;
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d_alusrc_b = ALUSRCB_RS2;
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d_aluop = ALUOP_ADD;
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d_memop = MEMOP_NONE;
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d_mulop = M_OP_MUL;
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d_csr_ren = 1'b0;
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d_csr_wen = 1'b0;
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d_csr_wtype = CSR_WTYPE_W;
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d_csr_w_imm = 1'b0;
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d_branchcond = BCOND_NEVER;
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d_addr_is_regoffs = 1'b0;
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d_invalid_32bit = 1'b0;
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d_except = EXCEPT_NONE;
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d_wfi = 1'b0;
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casez (d_instr)
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RV_BEQ: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_ZERO; end
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RV_BNE: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_NZERO; end
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RV_BLT: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_NZERO; end
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RV_BGE: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_ZERO; end
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RV_BLTU: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_NZERO; end
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RV_BGEU: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_ZERO; end
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RV_JALR: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_aluop = ALUOP_ADD; d_alusrc_a = ALUSRCA_PC; d_alusrc_b = ALUSRCB_IMM; d_imm = d_instr_is_32bit ? 32'h4 : 32'h2; end
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RV_JAL: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_rs1 = X0; d_rs2 = X0; d_aluop = ALUOP_ADD; d_alusrc_a = ALUSRCA_PC; d_alusrc_b = ALUSRCB_IMM; d_imm = d_instr_is_32bit ? 32'h4 : 32'h2; end
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RV_LUI: begin d_aluop = ALUOP_RS2; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_rs1 = X0; end
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RV_AUIPC: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_aluop = ALUOP_ADD; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_alusrc_a = ALUSRCA_PC; d_rs1 = X0; end
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RV_ADDI: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SLLI: begin d_aluop = ALUOP_SLL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SLTI: begin d_aluop = ALUOP_LT; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SLTIU: begin d_aluop = ALUOP_LTU; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_XORI: begin d_aluop = ALUOP_XOR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SRLI: begin d_aluop = ALUOP_SRL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SRAI: begin d_aluop = ALUOP_SRA; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_ORI: begin d_aluop = ALUOP_OR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_ANDI: begin d_aluop = ALUOP_AND; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_ADD: begin d_aluop = ALUOP_ADD; end
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RV_SUB: begin d_aluop = ALUOP_SUB; end
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RV_SLL: begin d_aluop = ALUOP_SLL; end
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RV_SLT: begin d_aluop = ALUOP_LT; end
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RV_SLTU: begin d_aluop = ALUOP_LTU; end
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RV_XOR: begin d_aluop = ALUOP_XOR; end
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RV_SRL: begin d_aluop = ALUOP_SRL; end
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RV_SRA: begin d_aluop = ALUOP_SRA; end
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RV_OR: begin d_aluop = ALUOP_OR; end
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RV_AND: begin d_aluop = ALUOP_AND; end
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RV_LB: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LB; end
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RV_LH: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LH; end
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RV_LW: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LW; end
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RV_LBU: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LBU; end
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RV_LHU: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LHU; end
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RV_SB: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SB; d_rd = X0; end
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RV_SH: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SH; d_rd = X0; end
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RV_SW: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SW; d_rd = X0; end
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RV_MUL: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MUL; end else begin d_invalid_32bit = 1'b1; end
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RV_MULH: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULH; end else begin d_invalid_32bit = 1'b1; end
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RV_MULHSU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHSU; end else begin d_invalid_32bit = 1'b1; end
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RV_MULHU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHU; end else begin d_invalid_32bit = 1'b1; end
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RV_DIV: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIV; end else begin d_invalid_32bit = 1'b1; end
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RV_DIVU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIVU; end else begin d_invalid_32bit = 1'b1; end
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RV_REM: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REM; end else begin d_invalid_32bit = 1'b1; end
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RV_REMU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REMU; end else begin d_invalid_32bit = 1'b1; end
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RV_LR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_LR_W; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_SC_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_SC_W; d_aluop = ALUOP_RS2; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOSWAP_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_RS2; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOADD_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_ADD; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOXOR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_XOR; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOAND_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_AND; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOOR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_OR; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOMIN_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MIN; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOMAX_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MAX; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOMINU_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MINU; end else begin d_invalid_32bit = 1'b1; end
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RV_AMOMAXU_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MAXU; end else begin d_invalid_32bit = 1'b1; end
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RV_SH1ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SH1ADD; end else begin d_invalid_32bit = 1'b1; end
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RV_SH2ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SH2ADD; end else begin d_invalid_32bit = 1'b1; end
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RV_SH3ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SH3ADD; end else begin d_invalid_32bit = 1'b1; end
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RV_ANDN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ANDN; end else begin d_invalid_32bit = 1'b1; end
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RV_CLZ: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CLZ; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_CPOP: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CPOP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_CTZ: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CTZ; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_MAX: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MAX; end else begin d_invalid_32bit = 1'b1; end
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RV_MAXU: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MAXU; end else begin d_invalid_32bit = 1'b1; end
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RV_MIN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MIN; end else begin d_invalid_32bit = 1'b1; end
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RV_MINU: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MINU; end else begin d_invalid_32bit = 1'b1; end
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RV_ORC_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ORC_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_ORN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ORN; end else begin d_invalid_32bit = 1'b1; end
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RV_REV8: if (EXTENSION_ZBB) begin d_aluop = ALUOP_REV8; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_ROL: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROL; end else begin d_invalid_32bit = 1'b1; end
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RV_ROR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROR; end else begin d_invalid_32bit = 1'b1; end
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RV_RORI: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROR; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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RV_SEXT_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_SEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_XNOR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_XNOR; end else begin d_invalid_32bit = 1'b1; end
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RV_ZEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ZEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_CLMUL: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end
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RV_CLMULH: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMULH; end else begin d_invalid_32bit = 1'b1; end
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RV_CLMULR: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMULR; end else begin d_invalid_32bit = 1'b1; end
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RV_BCLR: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BCLR; end else begin d_invalid_32bit = 1'b1; end
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RV_BCLRI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BCLR; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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RV_BEXT: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BEXT; end else begin d_invalid_32bit = 1'b1; end
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RV_BEXTI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BEXT; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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RV_BINV: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BINV; end else begin d_invalid_32bit = 1'b1; end
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RV_BINVI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BINV; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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RV_BSET: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; end else begin d_invalid_32bit = 1'b1; end
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RV_BSETI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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RV_PACK: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_PACK; end else begin d_invalid_32bit = 1'b1; end
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RV_PACKH: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_PACKH; end else begin d_invalid_32bit = 1'b1; end
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RV_BREV8: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_BREV8; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_UNZIP: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_UNZIP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_ZIP: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_ZIP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_FENCE: begin d_rs2 = X0; end // NOP, note rs1/rd are zero in instruction
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RV_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction
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RV_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRWI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRSI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRCI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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RV_ECALL: if (HAVE_CSR) begin d_except = m_mode || !U_MODE ? EXCEPT_ECALL_M : EXCEPT_ECALL_U; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_EBREAK: if (HAVE_CSR) begin d_except = EXCEPT_EBREAK; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_MRET: if (HAVE_CSR && m_mode) begin d_except = EXCEPT_MRET; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_WFI: if (HAVE_CSR && permit_wfi) begin d_wfi = 1'b1; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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default: begin d_invalid_32bit = 1'b1; end
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endcase
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if (d_invalid || d_starved || d_except_instr_bus_fault) begin
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d_rs1 = {W_REGADDR{1'b0}};
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d_rs2 = {W_REGADDR{1'b0}};
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d_rd = {W_REGADDR{1'b0}};
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d_memop = MEMOP_NONE;
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d_branchcond = BCOND_NEVER;
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d_csr_ren = 1'b0;
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d_csr_wen = 1'b0;
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d_except = EXCEPT_NONE;
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d_wfi = 1'b0;
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if (EXTENSION_M)
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d_aluop = ALUOP_ADD;
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if (d_except_instr_bus_fault)
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d_except = EXCEPT_INSTR_FAULT;
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else if (d_invalid && !d_starved)
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d_except = EXCEPT_INSTR_ILLEGAL;
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end
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if (cir_lock_prev) begin
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d_branchcond = BCOND_NEVER;
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end
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end
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endmodule
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