77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Register file
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// Single write port, dual read port
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`default_nettype none
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module hazard3_regfile_1w2r #(
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parameter RESET_REGS = 0, // Unsupported for FAKE_DUALPORT
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parameter N_REGS = 16,
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parameter W_DATA = 32,
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parameter W_ADDR = $clog2(W_DATA) // should be localparam. ISIM...
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) (
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input wire clk,
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input wire rst_n,
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input wire [W_ADDR-1:0] raddr1,
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output reg [W_DATA-1:0] rdata1,
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input wire [W_ADDR-1:0] raddr2,
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output reg [W_DATA-1:0] rdata2,
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input wire [W_ADDR-1:0] waddr,
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input wire [W_DATA-1:0] wdata,
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input wire wen
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);
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generate
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if (RESET_REGS) begin: real_dualport_reset
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// This will presumably always be implemented with flops
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reg [W_DATA-1:0] mem [0:N_REGS-1];
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integer i;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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for (i = 0; i < N_REGS; i = i + 1) begin
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mem[i] <= {W_DATA{1'b0}};
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end
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rdata1 <= {W_DATA{1'b0}};
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rdata2 <= {W_DATA{1'b0}};
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end else begin
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if (wen) begin
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mem[waddr] <= wdata;
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end
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rdata1 <= mem[raddr1];
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rdata2 <= mem[raddr2];
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end
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end
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end else begin: real_dualport_noreset
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// This should be inference-compatible on FPGAs with dual-port BRAMs
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`ifdef YOSYS
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`ifdef FPGA_ICE40
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// We do not require write-to-read bypass logic on the BRAM
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(* no_rw_check *)
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`endif
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`endif
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reg [W_DATA-1:0] mem [0:N_REGS-1];
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always @ (posedge clk) begin
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if (wen) begin
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mem[waddr] <= wdata;
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end
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rdata1 <= mem[raddr1];
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rdata2 <= mem[raddr2];
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end
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end
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endgenerate
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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