Luke Wren 78d937e5c8 Yeet Zcb into core		2023-03-16 18:48:15 +00:00
..
.gitignore	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
Makefile	Add config headers to tb_cxxrtl instead of using defparams in Makefile	2022-10-08 08:09:26 +01:00
compliance.cfg	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
config_default.vh	Yeet Zcb into core	2023-03-16 18:48:15 +00:00
config_min.vh	Yeet Zcb into core	2023-03-16 18:48:15 +00:00
gdbinit	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
multicore-openocd.cfg	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
multicore.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
openocd.cfg	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
tb.cpp	Allow reconnecting to the testbench JTAG socket	2022-12-17 11:58:14 +00:00
tb.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb.v	Increase DTM idle cycle hint to 8 cycles -- see #6	2022-10-19 21:11:18 +01:00
tb_common.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb_multicore.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb_multicore.v	Increase DTM idle cycle hint to 8 cycles -- see #6	2022-10-19 21:11:18 +01:00
waves.gtkw	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00