74 lines
4.9 KiB
Plaintext
74 lines
4.9 KiB
Plaintext
== Introduction
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Hazard3 is a configurable 3-stage RISC-V processor, implementing:
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* `RV32I`: 32-bit base instruction set
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* `M`: integer multiply/divide/modulo
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* `A`: atomic memory operations, with AHB5 global exclusives
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* `C`: compressed instructions
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* `Zicsr`: CSR access
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* `Zba`: address generation
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* `Zbb`: basic bit manipulation
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* `Zbc`: carry-less multiplication
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* `Zbs`: single-bit manipulation
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* `Zbkb`: basic bit manipulation for scalar cryptography
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* Debug, Machine and User privilege/execution modes
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* Privileged instructions `ECALL`, `EBREAK`, `MRET` and `WFI`
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* External debug support
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* Instruction address trigger unit (hardware breakpoints)
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=== Architectural Overview
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==== Pipe Stages
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The three stages are:
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* `F`: Fetch
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** Contains the data phase for instruction fetch
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** Contains the instruction prefetch buffer
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** Predecodes register numbers `rs1`/`rs2`, for faster register file read and register bypass
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* `X`: Execute
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** Decode and execute instructions
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** Drive the address phase for load/store/AMO
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** Generate jump/branch addresses
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* `M`: Memory
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** Contains the data phase for load/store/AMO
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** Register writeback is at the end of stage `M`
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** Generate exception addresses
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The instruction fetch address phase is best thought of as residing in stage `X`. The 2-cycle feedback loop between jump/branch decode into address issue in stage `X`, and the fetch data phase in stage `F`, is what defines Hazard3's jump/branch performance.
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==== Bus Interfaces
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Hazard3 implements either one or two AHB5 bus master ports. The single-port configuration is used when ease of integration is a priority, since it supports simpler bus topologies. The dual-port configuration adds a dedicated port for instruction fetch, which improves both the maximum frequency and the clock-for-clock performance.
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Hazard3 uses AHB5 specifically, rather than older versions of the AHB standard, because of its support for its global exclusives. This is a bus feature that allows a processor to perform an ordered read-modify-write sequence with a guarantee that no other processor has written to the same address range in between. Hazard3 uses this to implement multiprocessor support for the A (atomics) extension.
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==== Multiply/Divide
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For minimal M-extension support, Hazard3 instantiates a sequential multiply/divide circuit (restoring divide, naive repeated-addition multiply). Instructions stall in stage `X` until the multiply/divide completes. Optionally, the circuit can be unrolled by a small factor to produce multiple bits ber clock -- 2 or 4 is achievable in practice.
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A single-cycle multiplier can be instantiated, retiring either to stage 3 or stage 2 (configurable). By default only 32-bit `mul` is supported, which is by far the most common of the four multiply instructions.
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=== List of RISC-V Specifications
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These are links to the ratified versions of the base instruction set and extensions implemented by Hazard3.
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[%autowidth.stretch, options="header"]
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|===
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| Extension | Specification
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| `RV32I` v2.1 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `M` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `A` v2.1 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `C` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `Zicsr` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `Zifencei` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `Zba` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbb` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbc` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbs` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbkb` v1.0.1 | https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf[Scalar Cryptography ISA extensions 20220218]
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| Machine ISA v1.12 | https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf[Privileged Architecture 20211203]
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| Debug v0.13.2 | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf[RISC-V External Debug Support 20190322]
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|===
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