Luke Wren 449348f459 Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. ... Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.		2021-12-07 19:24:53 +00:00
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formal	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.	2021-12-07 19:24:53 +00:00
sim	Timer struct in IO header	2021-12-06 17:16:21 +00:00
.gitignore	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00