143 lines
4.8 KiB
C
143 lines
4.8 KiB
C
/*******************************************************************************
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* AUTOGENERATED BY REGBLOCK *
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* Do not edit manually. *
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* Edit the source file (or regblock utility) and regenerate. *
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*******************************************************************************/
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#ifndef _UART_REGS_H_
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#define _UART_REGS_H_
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// Block name : uart
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// Bus type : apb
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// Bus data width : 32
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// Bus address width : 16
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#define UART_CSR_OFFS 0
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#define UART_DIV_OFFS 4
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#define UART_FSTAT_OFFS 8
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#define UART_TX_OFFS 12
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#define UART_RX_OFFS 16
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/*******************************************************************************
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* CSR *
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*******************************************************************************/
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// Control and status register
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// Field: CSR_EN Access: RW
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// UART runs when en is high. Synchronous reset (excluding FIFOs) when low.
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#define UART_CSR_EN_LSB 0
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#define UART_CSR_EN_BITS 1
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#define UART_CSR_EN_MASK 0x1
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// Field: CSR_BUSY Access: ROV
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// UART TX is still sending data
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#define UART_CSR_BUSY_LSB 1
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#define UART_CSR_BUSY_BITS 1
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#define UART_CSR_BUSY_MASK 0x2
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// Field: CSR_TXIE Access: RW
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// Enable TX FIFO interrupt
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#define UART_CSR_TXIE_LSB 2
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#define UART_CSR_TXIE_BITS 1
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#define UART_CSR_TXIE_MASK 0x4
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// Field: CSR_RXIE Access: RW
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// Enable RX FIFO interrupt
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#define UART_CSR_RXIE_LSB 3
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#define UART_CSR_RXIE_BITS 1
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#define UART_CSR_RXIE_MASK 0x8
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// Field: CSR_CTSEN Access: RW
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// Enable pausing of TX while CTS is not asserted
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#define UART_CSR_CTSEN_LSB 4
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#define UART_CSR_CTSEN_BITS 1
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#define UART_CSR_CTSEN_MASK 0x10
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// Field: CSR_LOOPBACK Access: RW
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// Connect TX -> RX and RTS -> CTS internally (for testing).
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#define UART_CSR_LOOPBACK_LSB 8
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#define UART_CSR_LOOPBACK_BITS 1
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#define UART_CSR_LOOPBACK_MASK 0x100
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/*******************************************************************************
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* DIV *
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*******************************************************************************/
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// Clock divider control fields
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// Field: DIV_INT Access: WO
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#define UART_DIV_INT_LSB 4
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#define UART_DIV_INT_BITS 10
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#define UART_DIV_INT_MASK 0x3ff0
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// Field: DIV_FRAC Access: WO
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#define UART_DIV_FRAC_LSB 0
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#define UART_DIV_FRAC_BITS 4
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#define UART_DIV_FRAC_MASK 0xf
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/*******************************************************************************
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* FSTAT *
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*******************************************************************************/
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// FIFO status register
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// Field: FSTAT_TXLEVEL Access: ROV
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#define UART_FSTAT_TXLEVEL_LSB 0
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#define UART_FSTAT_TXLEVEL_BITS 8
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#define UART_FSTAT_TXLEVEL_MASK 0xff
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// Field: FSTAT_TXFULL Access: ROV
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#define UART_FSTAT_TXFULL_LSB 8
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#define UART_FSTAT_TXFULL_BITS 1
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#define UART_FSTAT_TXFULL_MASK 0x100
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// Field: FSTAT_TXEMPTY Access: ROV
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#define UART_FSTAT_TXEMPTY_LSB 9
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#define UART_FSTAT_TXEMPTY_BITS 1
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#define UART_FSTAT_TXEMPTY_MASK 0x200
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// Field: FSTAT_TXOVER Access: W1C
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#define UART_FSTAT_TXOVER_LSB 10
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#define UART_FSTAT_TXOVER_BITS 1
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#define UART_FSTAT_TXOVER_MASK 0x400
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// Field: FSTAT_TXUNDER Access: W1C
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#define UART_FSTAT_TXUNDER_LSB 11
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#define UART_FSTAT_TXUNDER_BITS 1
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#define UART_FSTAT_TXUNDER_MASK 0x800
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// Field: FSTAT_RXLEVEL Access: ROV
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#define UART_FSTAT_RXLEVEL_LSB 16
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#define UART_FSTAT_RXLEVEL_BITS 8
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#define UART_FSTAT_RXLEVEL_MASK 0xff0000
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// Field: FSTAT_RXFULL Access: ROV
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#define UART_FSTAT_RXFULL_LSB 24
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#define UART_FSTAT_RXFULL_BITS 1
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#define UART_FSTAT_RXFULL_MASK 0x1000000
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// Field: FSTAT_RXEMPTY Access: ROV
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#define UART_FSTAT_RXEMPTY_LSB 25
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#define UART_FSTAT_RXEMPTY_BITS 1
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#define UART_FSTAT_RXEMPTY_MASK 0x2000000
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// Field: FSTAT_RXOVER Access: W1C
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#define UART_FSTAT_RXOVER_LSB 26
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#define UART_FSTAT_RXOVER_BITS 1
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#define UART_FSTAT_RXOVER_MASK 0x4000000
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// Field: FSTAT_RXUNDER Access: W1C
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#define UART_FSTAT_RXUNDER_LSB 27
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#define UART_FSTAT_RXUNDER_BITS 1
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#define UART_FSTAT_RXUNDER_MASK 0x8000000
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/*******************************************************************************
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* TX *
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*******************************************************************************/
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// TX data FIFO
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// Field: TX Access: WF
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#define UART_TX_LSB 0
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#define UART_TX_BITS 8
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#define UART_TX_MASK 0xff
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/*******************************************************************************
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* RX *
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*******************************************************************************/
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// RX data FIFO
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// Field: RX Access: RF
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#define UART_RX_LSB 0
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#define UART_RX_BITS 8
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#define UART_RX_MASK 0xff
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#endif // _UART_REGS_H_
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