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Hazard3/test/sim/rvcpp
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Luke Wren e34aa5bb45 rvcpp: implement MPRV, and fix up CSR write tracing 2024-06-02 12:46:41 +01:00
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include rvcpp: implement MPRV, and fix up CSR write tracing 2024-06-02 12:46:41 +01:00
scripts Add trace disassembly annotation script for rvcpp, and add runtests support for passing flags to tb, and running post-processing commands on test results. 2024-06-02 11:20:58 +01:00
.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Add trace disassembly annotation script for rvcpp, and add runtests support for passing flags to tb, and running post-processing commands on test results. 2024-06-02 11:20:58 +01:00
main.cpp Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass. 2024-03-22 00:52:01 +00:00
rv_core.cpp rvcpp: implement MPRV, and fix up CSR write tracing 2024-06-02 12:46:41 +01:00
rv_csr.cpp rvcpp: implement MPRV, and fix up CSR write tracing 2024-06-02 12:46:41 +01:00