Luke Wren a79c857d82 Bump riscv-tests: enable hardware instruction breakpoints in hardware tests		2022-08-27 17:05:02 +01:00
..
riscv-tests@f465c797a2	Bump riscv-tests: enable hardware instruction breakpoints in hardware tests	2022-08-27 17:05:02 +01:00
debug.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
run-debug-tests.sh	Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant	2022-08-23 00:05:30 +01:00
run-isa-tests.sh	Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.	2022-05-28 17:22:28 +01:00
run-smp-debug-tests.sh	Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed	2022-07-03 23:34:12 +01:00