62 lines
2.0 KiB
Verilog
62 lines
2.0 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// Nothing to see here, just a sync FIFO
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module hazard3_uart_dtm_fifo #(
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parameter WIDTH = 8,
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parameter LOG_DEPTH = 2
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) (
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input wire clk,
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input wire rst_n,
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input wire [WIDTH-1:0] wdata,
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input wire wvld,
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output wire wrdy,
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output wire [WIDTH-1:0] rdata,
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output wire rvld,
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input wire rrdy
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);
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reg [WIDTH-1:0] fifo_mem [0:(1 << LOG_DEPTH) - 1];
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reg [LOG_DEPTH:0] wptr;
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reg [LOG_DEPTH:0] rptr;
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assign wrdy = (rptr ^ {1'b1, {LOG_DEPTH{1'b0}}}) != wptr;
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assign rvld = rptr != wptr;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wptr <= {LOG_DEPTH+1{1'b0}};
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rptr <= {LOG_DEPTH+1{1'b0}};
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end else begin
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if (wvld && wrdy) begin
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fifo_mem[wptr[LOG_DEPTH-1:0]] <= wdata;
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wptr <= wptr + 1'b1;
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end
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if (rvld && rrdy) begin
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rptr <= rptr + 1'b1;
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end
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end
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end
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assign rdata = fifo_mem[rptr[LOG_DEPTH-1:0]];
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endmodule
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