296 lines
9.8 KiB
Verilog
296 lines
9.8 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2018 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// Combined multiply/divide/modulo circuit.
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// All operations performed at 1 bit per clock; aiming for minimal resource usage.
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// There are lots of opportunities for off-by-one errors here. See muldiv_model.py
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// for a simple reference model of the mul/div/mod iterations.
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//
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// When op_kill is high, the current calculation halts immediately. op_vld can be
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// asserted on the same cycle, and the new calculation begins without delay, regardless
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// of op_rdy. This may be used by the processor on e.g. mispredict or trap.
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//
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// The actual multiply/divide hardware is unsigned. We handle signedness at
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// input/output.
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module hazard3_muldiv_seq #(
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parameter XLEN = 32,
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parameter UNROLL = 1,
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parameter W_CTR = $clog2(XLEN + 1), // do not modify
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`include "hazard3_width_const.vh"
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) (
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input wire clk,
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input wire rst_n,
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input wire [W_MULOP-1:0] op,
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input wire op_vld,
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output wire op_rdy,
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input wire op_kill,
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input wire [XLEN-1:0] op_a,
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input wire [XLEN-1:0] op_b,
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output wire [XLEN-1:0] result_h, // mulh* or rem*
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output wire [XLEN-1:0] result_l, // mul or div*
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output wire result_vld
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);
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`include "hazard3_ops.vh"
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//synthesis translate_off
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generate if (UNROLL & (UNROLL - 1) || ~|UNROLL)
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initial $fatal("%m: UNROLL must be a positive power of 2");
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endgenerate
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//synthesis translate_on
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// ----------------------------------------------------------------------------
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// Operation decode, operand sign adjustment
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// On the first cycle, op_a and op_b go straight through to the accumulator
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// and the divisor/multiplicand register. They are then adjusted in-place
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// on the next cycle. This allows the same circuits to be reused for sign
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// adjustment before output (and helps input timing).
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reg [W_MULOP-1:0] op_r;
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reg [2*XLEN-1:0] accum;
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reg [XLEN-1:0] op_b_r;
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reg op_a_neg_r;
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reg op_b_neg_r;
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wire op_a_signed =
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op_r == M_OP_MULH ||
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op_r == M_OP_MULHSU ||
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op_r == M_OP_DIV ||
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op_r == M_OP_REM;
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wire op_b_signed =
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op_r == M_OP_MULH ||
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op_r == M_OP_DIV ||
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op_r == M_OP_REM;
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wire op_a_neg = op_a_signed && accum[XLEN-1];
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wire op_b_neg = op_b_signed && op_b_r[XLEN-1];
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wire is_div = op_r[2];
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// Controls for modifying sign of all/part of accumulator
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wire accum_neg_l;
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wire accum_inv_h;
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wire accum_incr_h;
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// ----------------------------------------------------------------------------
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// Arithmetic circuit
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// Combinatorials:
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reg [2*XLEN-1:0] accum_next;
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reg [2*XLEN-1:0] addend;
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reg [2*XLEN-1:0] shift_tmp;
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reg [2*XLEN-1:0] addsub_tmp;
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reg neg_l_borrow;
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always @ (*) begin: alu
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integer i;
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// Multiply/divide iteration layers
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accum_next = accum;
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addend = {2*XLEN{1'b0}};
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addsub_tmp = {2*XLEN{1'b0}};
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neg_l_borrow = 1'b0;
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for (i = 0; i < UNROLL; i = i + 1) begin
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addend = {is_div && |op_b_r, op_b_r, {XLEN-1{1'b0}}};
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shift_tmp = is_div ? accum_next : accum_next >> 1;
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addsub_tmp = shift_tmp + addend;
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accum_next = (is_div ? !addsub_tmp[2 * XLEN - 1] : accum_next[0]) ?
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addsub_tmp : shift_tmp;
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if (is_div)
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accum_next = {accum_next[2*XLEN-2:0], !addsub_tmp[2 * XLEN - 1]};
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end
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// Alternative path for negation of all/part of accumulator
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if (accum_neg_l)
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{neg_l_borrow, accum_next[XLEN-1:0]} = {~accum[XLEN-1:0]} + 1'b1;
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if (accum_incr_h || accum_inv_h)
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accum_next[XLEN +: XLEN] = (accum[XLEN +: XLEN] ^ {XLEN{accum_inv_h}})
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+ accum_incr_h;
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end
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// ----------------------------------------------------------------------------
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// Main state machine
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reg sign_preadj_done;
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reg [W_CTR-1:0] ctr;
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reg sign_postadj_done;
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reg sign_postadj_carry;
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localparam CTR_TOP = XLEN[W_CTR-1:0];
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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ctr <= {W_CTR{1'b0}};
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sign_preadj_done <= 1'b1;
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sign_postadj_done <= 1'b1;
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sign_postadj_carry <= 1'b0;
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op_r <= {W_MULOP{1'b0}};
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op_a_neg_r <= 1'b0;
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op_b_neg_r <= 1'b0;
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op_b_r <= {XLEN{1'b0}};
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accum <= {XLEN*2{1'b0}};
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end else if (op_kill || (op_vld && op_rdy)) begin
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// Initialise circuit with operands + state
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ctr <= op_vld ? CTR_TOP : {W_CTR{1'b0}};
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sign_preadj_done <= !op_vld;
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sign_postadj_done <= !op_vld;
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sign_postadj_carry <= 1'b0;
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op_r <= op;
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op_b_r <= op_b;
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accum <= {{XLEN{1'b0}}, op_a};
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end else if (!sign_preadj_done) begin
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// Pre-adjust sign if necessary, else perform first iteration immediately
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op_a_neg_r <= op_a_neg;
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op_b_neg_r <= op_b_neg;
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sign_preadj_done <= 1'b1;
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if (accum_neg_l || (op_b_neg ^ is_div)) begin
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if (accum_neg_l)
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accum[0 +: XLEN] <= accum_next[0 +: XLEN];
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if (op_b_neg ^ is_div)
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op_b_r <= -op_b_r;
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end else begin
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ctr <= ctr - UNROLL[W_CTR-1:0];
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accum <= accum_next;
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end
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end else if (|ctr) begin
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ctr <= ctr - UNROLL[W_CTR-1:0];
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accum <= accum_next;
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end else if (!sign_postadj_done || sign_postadj_carry) begin
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sign_postadj_done <= 1'b1;
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if (accum_inv_h || accum_incr_h)
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accum[XLEN +: XLEN] <= accum_next[XLEN +: XLEN];
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if (accum_neg_l) begin
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accum[0 +: XLEN] <= accum_next[0 +: XLEN];
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if (!is_div) begin
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sign_postadj_carry <= neg_l_borrow;
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sign_postadj_done <= !neg_l_borrow;
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end
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end
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end
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end
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// ----------------------------------------------------------------------------
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// Sign adjustment control
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// Pre-adjustment: for any a, b we want |a|, |b|. Note that the magnitude of any
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// 32-bit signed integer is representable by a 32-bit unsigned integer.
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// Post-adjustment for division:
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// We seek q, r to satisfy a = b * q + r, where a and b are given,
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// and |r| < |b|. One way to do this is if
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// sgn(r) = sgn(a)
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// sgn(q) = sgn(a) ^ sgn(b)
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// This has additional nice properties like
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// -(a / b) = (-a) / b = a / (-b)
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// Post-adjustment for multiplication:
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// We have calculated the 2*XLEN result of |a| * |b|.
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// Negate the entire accumulator if sgn(a) ^ sgn(b).
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// This is done in two steps (to share div/mod circuit, and avoid 64-bit carry):
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// - Negate lower half of accumulator, and invert upper half
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// - Increment upper half if lower half carried
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wire do_postadj = ~|{ctr, sign_postadj_done};
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wire op_signs_differ = op_a_neg_r ^ op_b_neg_r;
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assign accum_neg_l =
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!sign_preadj_done && op_a_neg ||
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do_postadj && !sign_postadj_carry && op_signs_differ && !(is_div && ~|op_b_r);
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assign {accum_incr_h, accum_inv_h} =
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do_postadj && is_div && op_a_neg_r ? 2'b11 :
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do_postadj && !is_div && op_signs_differ && !sign_postadj_carry ? 2'b01 :
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do_postadj && !is_div && op_signs_differ && sign_postadj_carry ? 2'b10 :
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2'b00 ;
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// ----------------------------------------------------------------------------
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// Outputs
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assign op_rdy = ~|{ctr, accum_neg_l, accum_incr_h, accum_inv_h};
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assign result_vld = op_rdy;
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`ifndef RISCV_FORMAL_ALTOPS
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assign {result_h, result_l} = accum;
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`else
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// Provide arithmetically simpler alternative operations, to speed up formal checks
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always assert(XLEN == 32); // TODO may care about this one day
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reg [XLEN-1:0] fml_a_saved;
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reg [XLEN-1:0] fml_b_saved;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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fml_a_saved <= {XLEN{1'b0}};
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fml_b_saved <= {XLEN{1'b0}};
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end else if (op_vld && op_rdy) begin
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fml_a_saved <= op_a;
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fml_b_saved <= op_b;
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end
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end
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assign result_h =
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op_r == M_OP_MULH ? (fml_a_saved + fml_b_saved) ^ 32'hf6583fb7 :
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op_r == M_OP_MULHSU ? (fml_a_saved - fml_b_saved) ^ 32'hecfbe137 :
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op_r == M_OP_MULHU ? (fml_a_saved + fml_b_saved) ^ 32'h949ce5e8 :
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op_r == M_OP_REM ? (fml_a_saved - fml_b_saved) ^ 32'h8da68fa5 :
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op_r == M_OP_REMU ? (fml_a_saved - fml_b_saved) ^ 32'h3138d0e1 : 32'hdeadbeef;
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assign result_l =
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op_r == M_OP_MUL ? (fml_a_saved + fml_b_saved) ^ 32'h5876063e :
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op_r == M_OP_DIV ? (fml_a_saved - fml_b_saved) ^ 32'h7f8529ec :
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op_r == M_OP_DIVU ? (fml_a_saved - fml_b_saved) ^ 32'h10e8fd70 : 32'hdeadbeef;
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`endif
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// ----------------------------------------------------------------------------
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// Interface properties
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`ifdef FORMAL
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always @ (posedge clk) if (rst_n && $past(rst_n)) begin: properties
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integer i;
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reg alive;
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if ($past(op_rdy && !op_vld))
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assert(op_rdy);
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if (result_vld && $past(result_vld) && !$past(op_kill))
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assert($stable({result_h, result_l}));
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// Kill will halt an in-progress operation, but a new operation may be
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// asserted simultaneously with kill.
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if ($past(op_kill))
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assert(op_rdy == !$past(op_vld));
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// We should be periodically ready (liveness property), unless new operations
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// are forced in immediately, simultaneous with a kill, in which case there
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// is no intermediate ready state.
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alive = op_rdy || (op_kill && op_vld);
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for (i = 1; i <= XLEN / UNROLL + 3; i = i + 1)
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alive = alive || $past(op_rdy || (op_kill && op_vld), i);
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assert(alive);
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end
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`endif
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endmodule
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