369 lines
17 KiB
Verilog
369 lines
17 KiB
Verilog
/******************************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2019 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*****************************************************************************/
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module hazard3_decode #(
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire clk,
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input wire rst_n,
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input wire [31:0] fd_cir,
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input wire [1:0] fd_cir_vld,
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output wire [1:0] df_cir_use,
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output wire df_cir_lock,
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output reg d_jump_req,
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output reg [W_ADDR-1:0] d_jump_target,
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output wire [W_ADDR-1:0] d_pc, // FIXME only added for riscv-formal
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output wire d_stall,
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input wire x_stall,
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input wire flush_d_x,
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input wire f_jump_rdy,
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input wire f_jump_now,
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input wire [W_ADDR-1:0] f_jump_target,
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output reg [W_REGADDR-1:0] d_rs1, // combinatorial
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output reg [W_REGADDR-1:0] d_rs2, // combinatorial
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output reg [W_DATA-1:0] dx_imm,
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output reg [W_REGADDR-1:0] dx_rs1,
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output reg [W_REGADDR-1:0] dx_rs2,
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output reg [W_REGADDR-1:0] dx_rd,
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output reg [W_ALUSRC-1:0] dx_alusrc_a,
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output reg [W_ALUSRC-1:0] dx_alusrc_b,
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output reg [W_ALUOP-1:0] dx_aluop,
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output reg [W_MEMOP-1:0] dx_memop,
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output reg [W_MULOP-1:0] dx_mulop,
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output reg dx_csr_ren,
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output reg dx_csr_wen,
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output reg [1:0] dx_csr_wtype,
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output reg dx_csr_w_imm,
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output reg [W_BCOND-1:0] dx_branchcond,
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output reg [W_ADDR-1:0] dx_jump_target,
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output reg dx_jump_is_regoffs,
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output reg dx_result_is_linkaddr,
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output reg [W_ADDR-1:0] dx_pc,
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output reg [W_ADDR-1:0] dx_mispredict_addr,
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output reg [2:0] dx_except
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);
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`include "rv_opcodes.vh"
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`include "hazard3_ops.vh"
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localparam HAVE_CSR = CSR_M_MANDATORY || CSR_M_TRAP || CSR_COUNTER;
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// ----------------------------------------------------------------------------
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// Expand compressed instructions
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wire [31:0] d_instr;
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wire d_instr_is_32bit;
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wire d_invalid_16bit;
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reg d_invalid_32bit;
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wire d_invalid = d_invalid_16bit || d_invalid_32bit;
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hazard3_instr_decompress #(
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.PASSTHROUGH(!EXTENSION_C)
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) decomp (
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.instr_in (fd_cir),
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.instr_is_32bit (d_instr_is_32bit),
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.instr_out (d_instr),
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.invalid (d_invalid_16bit)
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);
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// Decode various immmediate formats
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wire [31:0] d_imm_i = {{21{d_instr[31]}}, d_instr[30:20]};
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wire [31:0] d_imm_s = {{21{d_instr[31]}}, d_instr[30:25], d_instr[11:7]};
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wire [31:0] d_imm_b = {{20{d_instr[31]}}, d_instr[7], d_instr[30:25], d_instr[11:8], 1'b0};
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wire [31:0] d_imm_u = {d_instr[31:12], {12{1'b0}}};
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wire [31:0] d_imm_j = {{12{d_instr[31]}}, d_instr[19:12], d_instr[20], d_instr[30:21], 1'b0};
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// ----------------------------------------------------------------------------
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// PC/CIR control
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wire d_starved = ~|fd_cir_vld || fd_cir_vld[0] && d_instr_is_32bit;
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assign d_stall = x_stall ||
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d_starved || (d_jump_req && !f_jump_rdy);
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assign df_cir_use =
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d_starved || d_stall ? 2'h0 :
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d_instr_is_32bit ? 2'h2 : 2'h1;
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// CIR Locking is required if we successfully assert a jump request, but decode is stalled.
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// (This only happens if decode stall is caused by X stall, not if fetch is starved!)
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// The reason for this is that, if the CIR is not locked in, it can be trashed by
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// incoming fetch data before the roadblock clears ahead of us, which will squash any other
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// side effects this instruction may have besides jumping! This includes:
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// - Linking for JAL
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// - Mispredict recovery for branches
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// Note that it is not possible to simply gate the jump request based on X stalling,
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// because X stall is a function of hready, and jump request feeds haddr htrans etc.
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// Note it is possible for d_jump_req and m_jump_req to be asserted
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// simultaneously, hence checking flush:
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wire jump_caused_by_d = d_jump_req && f_jump_rdy && !flush_d_x;
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wire assert_cir_lock = jump_caused_by_d && d_stall;
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wire deassert_cir_lock = !d_stall;
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reg cir_lock_prev;
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assign df_cir_lock = (cir_lock_prev && !deassert_cir_lock) || assert_cir_lock;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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cir_lock_prev <= 1'b0;
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else
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cir_lock_prev <= df_cir_lock;
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reg [W_ADDR-1:0] pc;
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wire [W_ADDR-1:0] pc_next = pc + (d_instr_is_32bit ? 32'h4 : 32'h2);
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assign d_pc = pc;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pc <= RESET_VECTOR;
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end else begin
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if ((f_jump_now && !assert_cir_lock) || (cir_lock_prev && deassert_cir_lock)) begin
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pc <= f_jump_target;
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`ifdef FORMAL
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// Being cheeky above to save a 32 bit mux. Check that we never get an M target by mistake.
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if (cir_lock_prev && deassert_cir_lock)
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assert(f_jump_target == d_jump_target);
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`endif
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end else if (!d_stall && !df_cir_lock) begin
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pc <= pc_next;
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end
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end
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end
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// If the current CIR is there due to locking, it is a jump which has already had primary effect.
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wire jump_enable = !d_starved && !cir_lock_prev && !d_invalid;
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reg [W_ADDR-1:0] d_jump_offs;
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always @ (*) begin
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// JAL is major opcode 1101111,
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// branches are 1100011.
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case (d_instr[3])
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1'b1: d_jump_offs = d_imm_j;
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default: d_jump_offs = d_imm_b;
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endcase
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d_jump_target = pc + d_jump_offs;
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casez ({d_instr[31], d_instr})
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{1'b1, RV_BEQ }: d_jump_req = jump_enable;
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{1'b1, RV_BNE }: d_jump_req = jump_enable;
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{1'b1, RV_BLT }: d_jump_req = jump_enable;
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{1'b1, RV_BGE }: d_jump_req = jump_enable;
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{1'b1, RV_BLTU}: d_jump_req = jump_enable;
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{1'b1, RV_BGEU}: d_jump_req = jump_enable;
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{1'bz, RV_JAL }: d_jump_req = jump_enable;
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default: d_jump_req = 1'b0;
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endcase
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end
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// ----------------------------------------------------------------------------
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// Decode X controls
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// Combinatorials:
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reg [W_REGADDR-1:0] d_rd;
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reg [W_DATA-1:0] d_imm;
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reg [W_DATA-1:0] d_branchoffs;
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reg [W_ALUSRC-1:0] d_alusrc_a;
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reg [W_ALUSRC-1:0] d_alusrc_b;
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reg [W_ALUOP-1:0] d_aluop;
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reg [W_MEMOP-1:0] d_memop;
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reg [W_MULOP-1:0] d_mulop;
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reg [W_BCOND-1:0] d_branchcond;
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reg d_jump_is_regoffs;
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reg d_result_is_linkaddr;
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reg d_csr_ren;
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reg d_csr_wen;
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reg [1:0] d_csr_wtype;
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reg d_csr_w_imm;
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reg [W_EXCEPT-1:0] d_except;
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localparam X0 = {W_REGADDR{1'b0}};
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always @ (*) begin
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// Assign some defaults
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d_rs1 = d_instr[19:15];
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d_rs2 = d_instr[24:20];
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d_rd = d_instr[11: 7];
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d_imm = d_imm_i;
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d_branchoffs = d_imm_i;
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d_alusrc_a = ALUSRCA_RS1;
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d_alusrc_b = ALUSRCB_RS2;
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d_aluop = ALUOP_ADD;
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d_memop = MEMOP_NONE;
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d_mulop = M_OP_MUL;
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d_csr_ren = 1'b0;
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d_csr_wen = 1'b0;
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d_csr_wtype = CSR_WTYPE_W;
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d_csr_w_imm = 1'b0;
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d_branchcond = BCOND_NEVER;
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d_jump_is_regoffs = 1'b0;
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d_result_is_linkaddr = 1'b0;
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d_invalid_32bit = 1'b0;
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d_except = EXCEPT_NONE;
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casez (d_instr)
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RV_BEQ: begin d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_ZERO; end
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RV_BNE: begin d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_NZERO; end
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RV_BLT: begin d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_NZERO; end
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RV_BGE: begin d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_ZERO; end
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RV_BLTU: begin d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_NZERO; end
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RV_BGEU: begin d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_ZERO; end
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RV_JALR: begin d_result_is_linkaddr = 1'b1; d_jump_is_regoffs = 1'b1; d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_branchcond = BCOND_ALWAYS; end
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RV_JAL: begin d_result_is_linkaddr = 1'b1; d_rs2 = X0; d_rs1 = X0; end
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RV_LUI: begin d_aluop = ALUOP_ADD; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_rs1 = X0; end
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RV_AUIPC: begin d_aluop = ALUOP_ADD; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_alusrc_a = ALUSRCA_PC; d_rs1 = X0; end
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RV_ADDI: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SLLI: begin d_aluop = ALUOP_SLL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SLTI: begin d_aluop = ALUOP_LT; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SLTIU: begin d_aluop = ALUOP_LTU; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_XORI: begin d_aluop = ALUOP_XOR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SRLI: begin d_aluop = ALUOP_SRL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_SRAI: begin d_aluop = ALUOP_SRA; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_ORI: begin d_aluop = ALUOP_OR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_ANDI: begin d_aluop = ALUOP_AND; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end
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RV_ADD: begin d_aluop = ALUOP_ADD; end
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RV_SUB: begin d_aluop = ALUOP_SUB; end
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RV_SLL: begin d_aluop = ALUOP_SLL; end
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RV_SLT: begin d_aluop = ALUOP_LT; end
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RV_SLTU: begin d_aluop = ALUOP_LTU; end
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RV_XOR: begin d_aluop = ALUOP_XOR; end
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RV_SRL: begin d_aluop = ALUOP_SRL; end
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RV_SRA: begin d_aluop = ALUOP_SRA; end
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RV_OR: begin d_aluop = ALUOP_OR; end
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RV_AND: begin d_aluop = ALUOP_AND; end
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RV_LB: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_memop = MEMOP_LB; end
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RV_LH: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_memop = MEMOP_LH; end
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RV_LW: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_memop = MEMOP_LW; end
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RV_LBU: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_memop = MEMOP_LBU; end
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RV_LHU: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_memop = MEMOP_LHU; end
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RV_SB: begin d_aluop = ALUOP_ADD; d_imm = d_imm_s; d_alusrc_b = ALUSRCB_IMM; d_memop = MEMOP_SB; d_rd = X0; end
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RV_SH: begin d_aluop = ALUOP_ADD; d_imm = d_imm_s; d_alusrc_b = ALUSRCB_IMM; d_memop = MEMOP_SH; d_rd = X0; end
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RV_SW: begin d_aluop = ALUOP_ADD; d_imm = d_imm_s; d_alusrc_b = ALUSRCB_IMM; d_memop = MEMOP_SW; d_rd = X0; end
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RV_MUL: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MUL; end else begin d_invalid_32bit = 1'b1; end
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RV_MULH: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULH; end else begin d_invalid_32bit = 1'b1; end
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RV_MULHSU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHSU; end else begin d_invalid_32bit = 1'b1; end
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RV_MULHU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHU; end else begin d_invalid_32bit = 1'b1; end
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RV_DIV: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIV; end else begin d_invalid_32bit = 1'b1; end
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RV_DIVU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIVU; end else begin d_invalid_32bit = 1'b1; end
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RV_REM: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REM; end else begin d_invalid_32bit = 1'b1; end
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RV_REMU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REMU; end else begin d_invalid_32bit = 1'b1; end
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RV_FENCE: begin d_rd = X0; end // NOP
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RV_FENCE_I: begin d_rd = X0; d_rs1 = X0; d_rs2 = X0; d_branchcond = BCOND_NZERO; d_imm[31] = 1'b1; end // Pretend we are recovering from a mispredicted-taken backward branch. Mispredict recovery flushes frontend.
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RV_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRWI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRSI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRCI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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RV_ECALL: if (HAVE_CSR) begin d_except = EXCEPT_ECALL; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_EBREAK: if (HAVE_CSR) begin d_except = EXCEPT_EBREAK; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_MRET: if (HAVE_CSR) begin d_except = EXCEPT_MRET; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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default: begin d_invalid_32bit = 1'b1; end
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endcase
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end
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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{dx_rs1, dx_rs2, dx_rd} <= {(3 * W_REGADDR){1'b0}};
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dx_alusrc_a <= ALUSRCA_RS1;
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dx_alusrc_b <= ALUSRCB_RS2;
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dx_aluop <= ALUOP_ADD;
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dx_memop <= MEMOP_NONE;
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dx_mulop <= M_OP_MUL;
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dx_csr_ren <= 1'b0;
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dx_csr_wen <= 1'b0;
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dx_csr_wtype <= CSR_WTYPE_W;
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dx_csr_w_imm <= 1'b0;
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dx_branchcond <= BCOND_NEVER;
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dx_jump_is_regoffs <= 1'b0;
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dx_result_is_linkaddr <= 1'b0;
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dx_except <= EXCEPT_NONE;
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end else if (flush_d_x || (d_stall && !x_stall)) begin
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// Bubble insertion
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dx_branchcond <= BCOND_NEVER;
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dx_memop <= MEMOP_NONE;
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dx_rd <= 5'h0;
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|
dx_except <= EXCEPT_NONE;
|
|
dx_csr_ren <= 1'b0;
|
|
dx_csr_wen <= 1'b0;
|
|
// Don't start a multiply in a pipe bubble
|
|
if (EXTENSION_M)
|
|
dx_aluop <= ALUOP_ADD;
|
|
// Also need to clear rs1, rs2, due to a nasty sequence of events:
|
|
// Suppose we have a load, followed by a dependent branch, which is predicted taken
|
|
// - branch will stall in D until AHB master becomes free
|
|
// - on next cycle, prediction causes jump, and bubble is in X
|
|
// - if X gets branch's rs1, rs2, it will cause spurious RAW stall
|
|
// - on next cycle, branch will not progress into X due to RAW stall, but *will* be replaced in D due to jump
|
|
// - branch mispredict now cannot be corrected
|
|
dx_rs1 <= 5'h0;
|
|
dx_rs2 <= 5'h0;
|
|
end else if (!x_stall) begin
|
|
// These ones can have side effects
|
|
dx_rs1 <= d_invalid ? {W_REGADDR{1'b0}} : d_rs1;
|
|
dx_rs2 <= d_invalid ? {W_REGADDR{1'b0}} : d_rs2;
|
|
dx_rd <= d_invalid ? {W_REGADDR{1'b0}} : d_rd;
|
|
dx_memop <= d_invalid ? MEMOP_NONE : d_memop;
|
|
dx_branchcond <= d_invalid ? BCOND_NEVER : d_branchcond;
|
|
dx_csr_ren <= d_invalid ? 1'b0 : d_csr_ren;
|
|
dx_csr_wen <= d_invalid ? 1'b0 : d_csr_wen;
|
|
dx_except <= d_invalid ? EXCEPT_INSTR_ILLEGAL : d_except;
|
|
dx_aluop <= d_invalid && EXTENSION_M ? ALUOP_ADD : d_aluop;
|
|
|
|
// These can't
|
|
dx_alusrc_a <= d_alusrc_a;
|
|
dx_alusrc_b <= d_alusrc_b;
|
|
dx_mulop <= d_mulop;
|
|
dx_jump_is_regoffs <= d_jump_is_regoffs;
|
|
dx_result_is_linkaddr <= d_result_is_linkaddr;
|
|
dx_csr_wtype <= d_csr_wtype;
|
|
dx_csr_w_imm <= d_csr_w_imm;
|
|
end
|
|
end
|
|
|
|
// No reset required on these; will be masked by the resettable pipeline controls until they're valid
|
|
always @ (posedge clk) begin
|
|
if (!x_stall) begin
|
|
dx_imm <= d_imm;
|
|
dx_jump_target <= d_jump_target;
|
|
dx_mispredict_addr <= pc_next;
|
|
dx_pc <= pc;
|
|
end
|
|
if (flush_d_x) begin
|
|
// The target of a late jump must be propagated *immediately* to X PC, as
|
|
// mepc may sample X PC at any time due to IRQ, and must not capture
|
|
// misprediction.
|
|
// Also required for flush while X stalled (e.g. if a muldiv enters X while
|
|
// a 1 cycle bus stall holds off the jump request in M)
|
|
dx_pc <= f_jump_target;
|
|
`ifdef FORMAL
|
|
// This should only be caused by late jumps
|
|
assert(f_jump_now);
|
|
`endif
|
|
end
|
|
end
|
|
|
|
endmodule
|