75 lines
1.9 KiB
Verilog
75 lines
1.9 KiB
Verilog
module rvfi_wrapper (
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input wire clock,
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input wire reset,
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`RVFI_OUTPUTS
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);
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// ----------------------------------------------------------------------------
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// Memory Interface
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// ----------------------------------------------------------------------------
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(* keep *) wire [31:0] haddr;
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(* keep *) wire hwrite;
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(* keep *) wire [1:0] htrans;
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(* keep *) wire [2:0] hsize;
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(* keep *) wire [2:0] hburst;
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(* keep *) wire [3:0] hprot;
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(* keep *) wire hmastlock;
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(* keep *) `rvformal_rand_reg hready;
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(* keep *) wire hresp;
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(* keep *) wire [31:0] hwdata;
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(* keep *) `rvformal_rand_reg [31:0] hrdata;
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// AHB-lite requires: data phase of IDLE has no wait states
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always @ (posedge clock)
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if ($past(htrans) == 2'b00 && $past(hready))
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assume(hready);
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// Handling of bus faults is not tested
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// always assume(!hresp);
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`ifdef RISCV_FORMAL_FAIRNESS
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reg [7:0] bus_fairness_ctr;
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localparam MAX_STALL_LENGTH = 8;
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always @ (posedge clock) begin
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if (reset)
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bus_fairness_ctr <= 8'h0;
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else if (hready)
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bus_fairness_ctr <= 8'h0;
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else
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bus_fairness_ctr <= bus_fairness_ctr + ~&bus_fairness_ctr;
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assume(bus_fairness_ctr <= MAX_STALL_LENGTH);
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end
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`endif
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// ----------------------------------------------------------------------------
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// Device Under Test
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// ----------------------------------------------------------------------------
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hazard3_cpu #(
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.RESET_VECTOR (0),
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.EXTENSION_C (1),
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.EXTENSION_M (1)
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) dut (
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.clk (clock),
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.rst_n (!reset),
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.ahblm_haddr (haddr),
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.ahblm_hwrite (hwrite),
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.ahblm_htrans (htrans),
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.ahblm_hsize (hsize),
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.ahblm_hburst (hburst),
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.ahblm_hprot (hprot),
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.ahblm_hmastlock (hmastlock),
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.ahblm_hready (hready),
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.ahblm_hresp (hresp),
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.ahblm_hwdata (hwdata),
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.ahblm_hrdata (hrdata),
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`RVFI_CONN
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);
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endmodule
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