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Hazard3/test/sim/tb_cxxrtl
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Luke Wren 9fb2af800f Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test 2021-12-12 14:58:50 +00:00
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.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Add test for identification CSRs vs expected values 2021-12-11 13:26:59 +00:00
compliance.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
gdbinit Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
openocd.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb.cpp Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test 2021-12-12 14:58:50 +00:00
tb.f Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb.v Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
waves.gtkw Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00