98 lines
3.3 KiB
Verilog
98 lines
3.3 KiB
Verilog
/******************************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*****************************************************************************/
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// Assumptions to constrain an AHB-Lite slave to be relatively well-behaved
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module ahbl_slave_assumptions #(
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parameter W_ADDR = 32,
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parameter W_DATA = 32,
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parameter MAX_BUS_STALL = -1 // set >= 0 to constrain max stall length
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) (
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input wire clk,
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input wire rst_n,
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input wire dst_hready_resp,
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input wire dst_hready,
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input wire dst_hresp,
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input wire [W_ADDR-1:0] dst_haddr,
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input wire dst_hwrite,
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input wire [1:0] dst_htrans,
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input wire [2:0] dst_hsize,
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input wire [2:0] dst_hburst,
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input wire [3:0] dst_hprot,
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input wire dst_hmastlock,
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input wire [W_DATA-1:0] dst_hwdata,
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input wire [W_DATA-1:0] dst_hrdata
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);
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reg dst_active_dph;
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reg dst_write_dph;
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reg [W_ADDR-1:0] dst_addr_dph;
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reg [2:0] dst_size_dph;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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dst_active_dph <= 1'b0;
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dst_write_dph <= 1'b0;
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dst_addr_dph <= {W_ADDR{1'b0}};
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dst_size_dph <= 3'h0;
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end else if (dst_hready) begin
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dst_active_dph <= dst_htrans[1];
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dst_write_dph <= dst_hwrite;
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dst_addr_dph <= dst_haddr;
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dst_size_dph <= dst_hsize;
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end
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end
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// Assumptions for all downstream responses
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always @ (posedge clk) if (rst_n) begin: dst_ahbl_resp_properties
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// IDLE->OKAY
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if (!dst_active_dph) begin
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assume(dst_hready_resp);
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assume(!dst_hresp);
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end
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// Correct two-phase error response.
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if (dst_hresp && dst_hready)
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assume($past(dst_hresp && !dst_hready));
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if (dst_hresp && !dst_hready)
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assume($past(!(dst_hresp && !dst_hready)));
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if ($past(dst_hresp && !dst_hready))
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assume(dst_hresp);
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end
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generate
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if (MAX_BUS_STALL >= 0) begin: constrain_max_bus_stall
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reg [7:0] bus_stall_ctr;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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bus_stall_ctr <= 8'h0;
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end else begin
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if (dst_hready)
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bus_stall_ctr <= 8'h0;
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else
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bus_stall_ctr <= bus_stall_ctr + ~&bus_stall_ctr;
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assume(bus_stall_ctr <= MAX_BUS_STALL);
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end
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end
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end
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endgenerate
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endmodule
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