284 lines
8.4 KiB
Verilog
284 lines
8.4 KiB
Verilog
// Assume bus responses to both ports are well-formed, assert that bus
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// requests are well-formed.
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`default_nettype none
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module tb;
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reg clk;
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reg rst_n = 1'b0;
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always @ (posedge clk)
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rst_n <= 1'b1;
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// ----------------------------------------------------------------------------
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// DUT
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(* keep *) wire pwrup_req;
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(* keep *) wire pwrup_ack;
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(* keep *) wire clk_en;
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(* keep *) wire unblock_out;
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(* keep *) wire unblock_in;
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(* keep *) wire [31:0] i_haddr;
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(* keep *) wire i_hwrite;
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(* keep *) wire [1:0] i_htrans;
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(* keep *) wire [2:0] i_hsize;
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(* keep *) wire [2:0] i_hburst;
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(* keep *) wire [3:0] i_hprot;
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(* keep *) wire i_hmastlock;
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(* keep *) wire i_hready;
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(* keep *) wire i_hresp;
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(* keep *) wire [31:0] i_hwdata;
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(* keep *) wire [31:0] i_hrdata;
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(* keep *) wire [31:0] d_haddr;
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(* keep *) wire d_hwrite;
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(* keep *) wire [1:0] d_htrans;
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(* keep *) wire [2:0] d_hsize;
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(* keep *) wire [2:0] d_hburst;
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(* keep *) wire [3:0] d_hprot;
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(* keep *) wire d_hmastlock;
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(* keep *) wire d_hexcl;
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(* keep *) wire d_hready;
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(* keep *) wire d_hresp;
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(* keep *) wire d_hexokay;
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(* keep *) wire [31:0] d_hwdata;
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(* keep *) wire [31:0] d_hrdata;
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localparam W_DATA = 32;
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(* keep *) wire dbg_req_halt;
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(* keep *) wire dbg_req_halt_on_reset;
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(* keep *) wire dbg_req_resume;
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(* keep *) wire dbg_halted;
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(* keep *) wire dbg_running;
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(* keep *) wire [W_DATA-1:0] dbg_data0_rdata;
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(* keep *) wire [W_DATA-1:0] dbg_data0_wdata;
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(* keep *) wire dbg_data0_wen;
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(* keep *) wire [W_DATA-1:0] dbg_instr_data;
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(* keep *) wire dbg_instr_data_vld;
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(* keep *) wire dbg_instr_data_rdy;
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(* keep *) wire dbg_instr_caught_exception;
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(* keep *) wire dbg_instr_caught_ebreak;
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(* keep *) wire [31:0] dbg_sbus_addr;
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(* keep *) wire dbg_sbus_write;
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(* keep *) wire [1:0] dbg_sbus_size;
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(* keep *) wire dbg_sbus_vld;
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(* keep *) wire dbg_sbus_rdy;
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(* keep *) wire dbg_sbus_err;
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(* keep *) wire [31:0] dbg_sbus_wdata;
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(* keep *) wire [31:0] dbg_sbus_rdata;
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(* keep *) wire [31:0] irq;
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(* keep *) wire soft_irq;
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(* keep *) wire timer_irq;
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hazard3_cpu_2port dut (
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.clk (clk),
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.clk_always_on (clk),
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.rst_n (rst_n),
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.pwrup_req (pwrup_req),
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.pwrup_ack (pwrup_ack),
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.clk_en (clk_en),
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.unblock_out (unblock_out),
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.unblock_in (unblock_in),
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.i_haddr (i_haddr),
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.i_hwrite (i_hwrite),
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.i_htrans (i_htrans),
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.i_hsize (i_hsize),
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.i_hburst (i_hburst),
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.i_hprot (i_hprot),
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.i_hmastlock (i_hmastlock),
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.i_hready (i_hready),
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.i_hresp (i_hresp),
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.i_hwdata (i_hwdata),
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.i_hrdata (i_hrdata),
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.d_haddr (d_haddr),
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.d_hwrite (d_hwrite),
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.d_htrans (d_htrans),
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.d_hsize (d_hsize),
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.d_hburst (d_hburst),
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.d_hprot (d_hprot),
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.d_hmastlock (d_hmastlock),
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.d_hexcl (d_hexcl),
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.d_hready (d_hready),
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.d_hresp (d_hresp),
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.d_hexokay (d_hexokay),
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.d_hwdata (d_hwdata),
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.d_hrdata (d_hrdata),
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.dbg_req_halt (dbg_req_halt),
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.dbg_req_halt_on_reset (dbg_req_halt_on_reset),
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.dbg_req_resume (dbg_req_resume),
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.dbg_halted (dbg_halted),
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.dbg_running (dbg_running),
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.dbg_data0_rdata (dbg_data0_rdata),
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.dbg_data0_wdata (dbg_data0_wdata),
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.dbg_data0_wen (dbg_data0_wen),
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.dbg_instr_data (dbg_instr_data),
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.dbg_instr_data_vld (dbg_instr_data_vld),
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.dbg_instr_data_rdy (dbg_instr_data_rdy),
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.dbg_instr_caught_exception (dbg_instr_caught_exception),
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.dbg_instr_caught_ebreak (dbg_instr_caught_ebreak),
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.dbg_sbus_addr (dbg_sbus_addr),
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.dbg_sbus_write (dbg_sbus_write),
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.dbg_sbus_size (dbg_sbus_size),
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.dbg_sbus_vld (dbg_sbus_vld),
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.dbg_sbus_rdy (dbg_sbus_rdy),
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.dbg_sbus_err (dbg_sbus_err),
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.dbg_sbus_wdata (dbg_sbus_wdata),
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.dbg_sbus_rdata (dbg_sbus_rdata),
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.irq (irq),
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.soft_irq (soft_irq),
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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// Power signal properties
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(* keep *) wire pwrup_ack_nxt;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pwrup_ack <= 1'b1;
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end else begin
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pwrup_ack <= 1'b1;
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end
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end
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always @ (posedge clk) if (rst_n) begin
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// Assume the testbench gives fair acks to the processor's reqs
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if (pwrup_req && pwrup_ack) begin
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assume(pwrup_ack_nxt);
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end
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if (!pwrup_req && !pwrup_ack) begin
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assume(!pwrup_ack_nxt);
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end
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// Assume there is no sbus access when powered down
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if (!(pwrup_req && pwrup_ack && clk_en)) begin
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assume(!dbg_sbus_vld);
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end
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// Assert only one of pwrup_req and pwrup_ack changes on one cycle
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// (processor upholds its side of the 4-phase handshake)
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assert((pwrup_ack != $past(pwrup_ack)) + {1'b0, (pwrup_req != $past(pwrup_req))} < 2'd2);
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// Assert processor doesn't access the bus whilst asleep
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if (!(pwrup_req && pwrup_ack && clk_en)) begin
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assert(i_htrans == 2'h0);
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assert(d_htrans == 2'h0);
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end
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end
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// ----------------------------------------------------------------------------
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// Bus properties
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// -1 -> unconstrained, >=0 -> max length
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localparam MAX_BUS_STALL = -1;
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ahbl_slave_assumptions #(
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.MAX_BUS_STALL (MAX_BUS_STALL)
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) i_assumptions (
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.clk (clk),
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.rst_n (rst_n),
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.dst_hready_resp (i_hready),
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.dst_hready (i_hready),
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.dst_hresp (i_hresp),
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.dst_hexokay (1'b0),
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.dst_haddr (i_haddr),
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.dst_hwrite (i_hwrite),
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.dst_htrans (i_htrans),
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.dst_hsize (i_hsize),
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.dst_hburst (i_hburst),
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.dst_hprot (i_hprot),
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.dst_hmastlock (i_hmastlock),
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.dst_hexcl (1'b0),
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.dst_hwdata (i_hwdata),
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.dst_hrdata (i_hrdata)
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);
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ahbl_slave_assumptions #(
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.MAX_BUS_STALL (MAX_BUS_STALL)
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) d_assumptions (
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.clk (clk),
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.rst_n (rst_n),
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.dst_hready_resp (d_hready),
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.dst_hready (d_hready),
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.dst_hresp (d_hresp),
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.dst_hexokay (d_hexokay),
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.dst_haddr (d_haddr),
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.dst_hwrite (d_hwrite),
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.dst_htrans (d_htrans),
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.dst_hsize (d_hsize),
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.dst_hburst (d_hburst),
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.dst_hprot (d_hprot),
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.dst_hmastlock (d_hmastlock),
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.dst_hexcl (d_hexcl),
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.dst_hwdata (d_hwdata),
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.dst_hrdata (d_hrdata)
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);
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ahbl_master_assertions i_assertions (
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.clk (clk),
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.rst_n (rst_n),
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.src_hready (i_hready),
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.src_hresp (i_hresp),
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.src_hexokay (1'b0),
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.src_haddr (i_haddr),
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.src_hwrite (i_hwrite),
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.src_htrans (i_htrans),
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.src_hsize (i_hsize),
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.src_hburst (i_hburst),
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.src_hprot (i_hprot),
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.src_hmastlock (i_hmastlock),
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.src_hexcl (1'b0),
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.src_hwdata (i_hwdata),
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.src_hrdata (i_hrdata)
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);
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ahbl_master_assertions d_assertions (
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.clk (clk),
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.rst_n (rst_n),
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.src_hready (d_hready),
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.src_hresp (d_hresp),
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.src_hexokay (d_hexokay),
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.src_haddr (d_haddr),
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.src_hwrite (d_hwrite),
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.src_htrans (d_htrans),
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.src_hsize (d_hsize),
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.src_hburst (d_hburst),
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.src_hprot (d_hprot),
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.src_hmastlock (d_hmastlock),
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.src_hexcl (d_hexcl),
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.src_hwdata (d_hwdata),
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.src_hrdata (d_hrdata)
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);
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sbus_assumptions sbus_assumptions (
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.clk (clk),
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.rst_n (rst_n),
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.dbg_sbus_addr (dbg_sbus_addr),
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.dbg_sbus_write (dbg_sbus_write),
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.dbg_sbus_size (dbg_sbus_size),
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.dbg_sbus_vld (dbg_sbus_vld),
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.dbg_sbus_rdy (dbg_sbus_rdy),
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.dbg_sbus_err (dbg_sbus_err),
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.dbg_sbus_wdata (dbg_sbus_wdata),
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.dbg_sbus_rdata (dbg_sbus_rdata)
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);
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endmodule
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