99 lines
3.5 KiB
Verilog
99 lines
3.5 KiB
Verilog
/******************************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*****************************************************************************/
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// Assert that an AHB-Lite master is relatively well-behaved
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module ahbl_master_assertions #(
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parameter W_ADDR = 32,
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parameter W_DATA = 32
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) (
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input wire clk,
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input wire rst_n,
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// Upstream AHB-Lite slave port
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output wire src_hready_resp,
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input wire src_hready,
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output wire src_hresp,
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input wire [W_ADDR-1:0] src_haddr,
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input wire src_hwrite,
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input wire [1:0] src_htrans,
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input wire [2:0] src_hsize,
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input wire [2:0] src_hburst,
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input wire [3:0] src_hprot,
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input wire src_hmastlock,
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input wire [W_DATA-1:0] src_hwdata,
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output wire [W_DATA-1:0] src_hrdata
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);
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// Data-phase monitoring
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reg src_active_dph;
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reg src_write_dph;
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reg [W_ADDR-1:0] src_addr_dph;
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reg [2:0] src_size_dph;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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src_active_dph <= 1'b0;
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src_write_dph <= 1'b0;
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src_addr_dph <= {W_ADDR{1'b0}};
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src_size_dph <= 3'h0;
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end else if (src_hready) begin
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src_active_dph <= src_htrans[1];
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src_write_dph <= src_hwrite;
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src_addr_dph <= src_haddr;
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src_size_dph <= src_hsize;
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end
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end
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// Assertions for all downstream requests
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always @ (posedge clk) if (rst_n) begin: dst_ahbl_req_properties
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// Address phase properties (inactive when request is IDLE):
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if (src_htrans != 2'b00) begin
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// Transfer must be naturally aligned
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assert(!(src_haddr & ~({W_ADDR{1'b1}} << src_hsize)));
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// HSIZE appropriate for bus width
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assert(8 << src_hsize <= W_DATA);
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// No deassertion or change of active request
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if ($past(src_htrans[1] && !src_hready)) begin
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assert($stable({
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src_htrans,
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src_hwrite,
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src_haddr,
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src_hsize,
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src_hburst,
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src_hprot,
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src_hmastlock
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}));
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end
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// SEQ only issued following an NSEQ or SEQ, never an IDLE
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if (src_htrans == 2'b11)
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assert(src_active_dph);
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// SEQ transfer addresses must be sequential with previous transfer (note
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// this only supports INCRx bursts)
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if (src_htrans == 2'b11)
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assert(src_haddr == src_addr_dph + W_DATA / 8);
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end
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// Data phase properties:
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if (src_active_dph) begin
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// Write data stable during write data phase
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if (src_write_dph && !$past(src_hready))
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assert($stable(src_hwdata));
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end
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end
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