19 lines
768 B
Plaintext
19 lines
768 B
Plaintext
== Introduction
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Hazard3 is a 3-stage RISC-V processor, providing the following architectural support:
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* `RV32I`: 32-bit base instruction set
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* `M` extension: integer multiply/divide/modulo
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* `C` extension: compressed instructions
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* `Zicsr` extension: CSR access
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* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET`
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* The machine-mode (M-mode) privilege state, and standard M-mode CSRs
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* Debug support, fully compliant with version 0.13.2 of the RISC-V external debug specification
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The following are planned for future implementation:
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* Support for `WFI` instruction
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* `A` extension: atomic memory access
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** `LR`/`SC` fully supported
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** AMONone PMA on all of memory (AMOs are decoded but unconditionally trigger access fault without attempting memory access)
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