76 lines
2.6 KiB
Verilog
76 lines
2.6 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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module hazard3_mul_fast #(
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parameter XLEN = 32
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) (
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input wire clk,
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input wire rst_n,
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input wire [XLEN-1:0] op_a,
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input wire [XLEN-1:0] op_b,
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input wire op_vld,
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output wire [XLEN-1:0] result,
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output reg result_vld
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);
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// This pipestage is folded into the front of the DSP tiles on UP5k. Note the
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// intention is to register the bypassed core regs at the end of X (since
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// bypass is quite slow), then perform multiply combinatorially in stage M,
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// and mux into MW result register.
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reg [XLEN-1:0] op_a_r;
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reg [XLEN-1:0] op_b_r;
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always @ (posedge clk) begin
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if (op_vld) begin
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op_a_r <= op_a;
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op_b_r <= op_b;
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end
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end
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// This should be inferred as 3 DSP tiles on UP5k:
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//
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// 1. Register then multiply a[15: 0] and b[15: 0]
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// 2. Register then multiply a[31:16] and b[15: 0], then directly add output of 1
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// 3. Register then multiply a[15: 0] and b[31:16], then directly add output of 2
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//
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// So there is quite a long path (1x 16-bit multiply, then 2x 16-bit add). On
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// other platforms you may just end up with a pile of gates.
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`ifndef RISCV_FORMAL_ALTOPS
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assign result = op_a_r * op_b_r;
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`else
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// riscv-formal can use a simpler function, since it's just confirming the
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// result is correctly hooked up.
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assign result = result_vld ? (op_a_r + op_b_r) ^ 32'h5876063e : 32'hdeadbeef;
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`endif
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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result_vld <= 1'b0;
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end else begin
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result_vld <= op_vld;
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end
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end
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endmodule
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