71 lines
2.0 KiB
Verilog
71 lines
2.0 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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`default_nettype none
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module fpga_ulx3s (
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input wire clk_osc,
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output wire [7:0] dbg,
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output wire uart_tx,
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input wire uart_rx
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);
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wire clk_sys;
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wire pll_sys_locked;
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wire rst_n_sys;
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pll_25_40 pll_sys (
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.clkin (clk_osc),
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.clkout0 (clk_sys),
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.locked (pll_sys_locked)
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);
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fpga_reset #(
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.SHIFT (3)
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) rstgen (
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.clk (clk_sys),
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.force_rst_n (pll_sys_locked),
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.rst_n (rst_n_sys)
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);
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example_soc #(
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.DTM_TYPE ("ECP5"),
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.SRAM_DEPTH (1 << 15),
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.EXTENSION_C (0),
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.EXTENSION_M (1),
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.CSR_COUNTER (1),
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.MUL_FAST (1),
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.MULDIV_UNROLL (2)
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) soc_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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// JTAG connections provided internally by ECP5 JTAGG primitive
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.tck (1'b0),
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.trst_n (1'b0),
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.tms (1'b0),
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.tdi (1'b0),
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.tdo (/* unused */),
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.uart_tx (uart_tx),
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.uart_rx (uart_rx)
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);
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endmodule
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