Hazard3/test/formal
Luke Wren 23b4dbe7f3 Redesign fetch queue: 2x32 + 3x16 -> 6x16.
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
..
bus_compliance_1port Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus. 2021-12-18 15:41:05 +00:00
bus_compliance_2port Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus. 2021-12-18 15:41:05 +00:00
common Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus. 2021-12-18 15:41:05 +00:00
frontend_fetch_match Redesign fetch queue: 2x32 + 3x16 -> 6x16. 2022-06-12 02:44:08 +01:00
instruction_fetch_match Redesign fetch queue: 2x32 + 3x16 -> 6x16. 2022-06-12 02:44:08 +01:00
riscv-formal RVFI monitor: blank out instructions which experienced an instruction fetch fault. 2022-04-12 13:38:19 +01:00
.gitignore Add simple formal bus properties check 2021-05-30 10:19:42 +01:00