Luke Wren cbb490da6a Bump riscv-tests for hazard3 SMP debug test config changes		2023-03-24 18:11:08 +00:00
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riscv-tests@5b04c5b81b	Bump riscv-tests for hazard3 SMP debug test config changes	2023-03-24 18:11:08 +00:00
debug.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
run-debug-tests.sh	Fix up HwbpManual test in riscv-tests fork, and update debug test list	2023-03-24 00:28:02 +00:00
run-isa-tests.sh	Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.	2022-05-28 17:22:28 +01:00
run-smp-debug-tests.sh	Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed	2022-07-03 23:34:12 +01:00