Luke Wren b1225c386c Add missing 1port SBA change, and update example soc and bus compliance tb to reflect		2022-07-03 17:57:03 +01:00
..
bus_compliance_1port	Add missing 1port SBA change, and update example soc and bus compliance tb to reflect	2022-07-03 17:57:03 +01:00
bus_compliance_2port	Add SBA patch-through to 1-core wrapper.	2022-07-03 15:17:44 +01:00
common	Add SBA patch-through to 1-core wrapper.	2022-07-03 15:17:44 +01:00
frontend_fetch_match	First pass at adding branch prediction	2022-06-15 02:05:46 +01:00
instruction_fetch_match	Reduce ROM size in instruction_fetch_match: depth is more useful	2022-06-26 19:59:44 +01:00
riscv-formal	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
.gitignore	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00