Luke Wren f48177c644 Tie off debug LEDs in ULX3S top level		2022-09-05 00:37:44 +01:00
..
fpga_icebreaker.f	Add activity LED to iCEBreaker	2021-07-25 13:13:41 +01:00
fpga_icebreaker.v	Example soc: connect up power signals and always-on clock. Set more parameters explicitly.	2022-09-04 23:42:48 +01:00
fpga_ulx3s.f	Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k	2021-07-25 13:41:04 +01:00
fpga_ulx3s.v	Tie off debug LEDs in ULX3S top level	2022-09-05 00:37:44 +01:00
pll_25_40.v	Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k	2021-07-25 13:41:04 +01:00
pll_25_50.v	Tweaks to example soc configuration	2021-07-23 23:08:23 +01:00