92 lines
7.2 KiB
Plaintext
92 lines
7.2 KiB
Plaintext
== Introduction
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Hazard3 is a configurable 3-stage RISC-V processor, implementing:
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* `RV32I`: 32-bit base instruction set
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* `M`: integer multiply/divide/modulo
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* `A`: atomic memory operations, with AHB5 global exclusives
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* `C`: compressed instructions
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* `Zicsr`: CSR access
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* `Zba`: address generation
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* `Zbb`: basic bit manipulation
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* `Zbc`: carry-less multiplication
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* `Zbs`: single-bit manipulation
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* `Zbkb`: basic bit manipulation for scalar cryptography
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* `Zcb`: basic additional compressed instructions
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* `Zcmp`: push/pop and double-move compressed instructions
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* Debug, Machine and User privilege/execution modes
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* Privileged instructions `ECALL`, `EBREAK`, `MRET` and `WFI`
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* External debug support
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* Instruction address trigger unit (hardware breakpoints)
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=== Architectural Overview
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==== Pipeline Stages
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The three stages are:
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* `F`: Fetch
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** Contains the data phase for instruction fetch
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** Contains the instruction prefetch buffer
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** Predecodes register numbers `rs1`/`rs2`, for faster register file read and register bypass
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** Contains the address match logic for the optional branch predictor
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* `X`: Execute
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** Decodes and execute instructions
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** Drives the address phase for load/store/AMO
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** Generates jump/branch addresses
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** Contains the read and write ports for the CSR file
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** Unbypassed register values are available at the beginning of stage `X`
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** The ALU result is valid by the end of stage `X`
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* `M`: Memory
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** Contains the data phase for load/store/AMO
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** Generates exception addresses
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** Register writeback is at the end of stage `M`
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The instruction fetch address phase is best thought of as residing in stage `X`. The 2-cycle feedback loop between jump/branch decode into address issue in stage `X`, and the fetch data phase in stage `F`, is what defines Hazard3's jump/branch performance.
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This document often refers to `F`, `X` and `M` as stages 1, 2 and 3 respectively. This numbering is useful when describing dependencies between values held in different pipeline stages, as it makes the direction and distance of the dependency more apparent.
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==== Bus Interfaces
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Hazard3 implements either one or two AHB5 bus manager ports. Use the single-port configuration when ease of integration is a priority, since it supports simpler bus topologies. The dual-port configuration adds a dedicated port for instruction fetch. Use the dual-port configuration for maximum frequency and the best clock-for-clock performance.
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Hazard3 uses AHB5 specifically, rather than older versions of the AHB standard, because of its support for global exclusives. This is a bus feature that allows a processor to perform an ordered read-modify-write sequence with a guarantee that no other processor has written to the same address range in between. Hazard3 uses this to implement multiprocessor support for the A (atomics) extension. Single-processor support for the A extension does not require these additional signals.
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AHB5 is one of the two protocols described in the https://documentation-service.arm.com/static/5f91607cf86e16515cdc3b4b[AMBA 5 AHB protocol specification]. Its full name is (perhaps surprisingly) AMBA 5 AHB5. Refer to the protocol specification for more information about this standard bus protocol.
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==== Multiply/Divide
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For minimal M-extension support, as enabled by <<param-EXTENSION_M>>, Hazard3 instantiates a sequential multiply/divide circuit (restoring divide, naive repeated-addition multiply). Instructions stall in stage `X` until the multiply/divide completes. Optionally, the circuit can be unrolled by a small factor to produce multiple bits ber clock. A throughput of one, two or four bits per cycle is achievable in practice, with the internal logic delay becoming quite significant at four.
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Set <<param-MUL_FAST>> to instantiate the single-cycle multiplier circuit. The fast multiplier returns results either to stage 3 or stage 2, depending on the <<param-MUL_FASTER>> parameter.
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By default the single-cycle multiplier only supports 32-bit `mul`, which is by far the most common of the four multiply instructions. The remaining instructions still execute on the sequential multiply/divide circuit. Set the <<param-MULH_FAST>> parameter to add single-cycle support for the high-half instructions (`mulh`, `mulhu` and `mulhsu`), at the cost of additional logic delay and area.
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The single-cycle multiplier is implemented as a simple `*` behavioural multiply, so that your tools can infer the best multiply circuit for your platform. For example, Yosys infers DSP tiles on iCE40 UP5k FPGAs. The multiplier is a self-contained module (in `hdl/arith/hazard3_mul_fast.v`), so you can replace its implementation if you know of a faster or lower-area method for your platform.
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// ** magic comment to reset sublime text asciidoc lexer
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=== List of RISC-V Specifications
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These are links to the ratified versions of the base instruction set and extensions implemented by Hazard3.
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[%autowidth.stretch, options="header"]
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|===
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| Extension | Specification
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| `RV32I` v2.1 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `M` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `A` v2.1 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `C` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `Zicsr` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `Zifencei` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
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| `Zba` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbb` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbc` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbs` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
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| `Zbkb` v1.0.1 | https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf[Scalar Cryptography ISA extensions 20220218]
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| `Zcb` v1.0.3-1 | https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3-1/Zc-v1.0.3-1.pdf[Code Size Reduction extensions frozen v1.0.3-1]
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| `Zcmp` v1.0.3-1 | https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3-1/Zc-v1.0.3-1.pdf[Code Size Reduction extensions frozen v1.0.3-1]
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| Machine ISA v1.12 | https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf[Privileged Architecture 20211203]
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| Debug v0.13.2 | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf[RISC-V External Debug Support 20190322]
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|===
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