34 lines
911 B
Verilog
34 lines
911 B
Verilog
/*****************************************************************************\
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| Copyright (C) 2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// req: bitmap
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// idx: bitmap with all bits clear except the least- (HIGHEST_WINS=0) or
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// most- (HIGHEST_WINS=1) significant set bit in req.
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`default_nettype none
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module hazard3_onehot_priority #(
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parameter W_REQ = 16,
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parameter HIGHEST_WINS = 0
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) (
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input wire [W_REQ-1:0] req,
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output reg [W_REQ-1:0] gnt
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);
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always @ (*) begin: select
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integer i;
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for (i = 0; i < W_REQ; i = i + 1) begin
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gnt[i] = req[i] && ~|(req & (
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HIGHEST_WINS ? ~({W_REQ{1'b1}} >> (W_REQ - 1 - i)) : ~({W_REQ{1'b1}} << i)
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));
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end
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end
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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