42 lines
964 B
Verilog
42 lines
964 B
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// req: bitmap
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// gnt: index of least set bit (HIGHEST_WINS=0) or most set bit (HIGHEST_WINS=1)
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`default_nettype none
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module hazard3_priority_encode #(
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parameter W_REQ = 16,
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parameter HIGHEST_WINS = 0,
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parameter W_GNT = $clog2(W_REQ) // do not modify
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) (
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input wire [W_REQ-1:0] req,
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output wire [W_GNT-1:0] gnt
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);
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wire [W_REQ-1:0] gnt_onehot;
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hazard3_onehot_priority #(
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.W_REQ (W_REQ),
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.HIGHEST_WINS (HIGHEST_WINS)
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) priority_u (
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.req (req),
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.gnt (gnt_onehot)
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);
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hazard3_onehot_encode #(
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.W_REQ (W_REQ)
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) encode_u (
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.req (gnt_onehot),
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.gnt (gnt)
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);
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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