67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Implement the three shifts (left logical, right logical, right arithmetic)
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// using a single log-type barrel shifter. Around 240 LUTs for 32 bits.
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// (7 layers of 32 2-input muxes, some extra LUTs and LUT inputs used for arith)
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`default_nettype none
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module hazard3_shift_barrel #(
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire [W_DATA-1:0] din,
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input wire [W_SHAMT-1:0] shamt,
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input wire right_nleft,
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input wire rotate,
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input wire arith,
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output reg [W_DATA-1:0] dout
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);
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reg [W_DATA-1:0] din_rev;
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reg [W_DATA-1:0] shift_accum;
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reg sext; // haha
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always @ (*) begin: shift
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integer i;
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for (i = 0; i < W_DATA; i = i + 1)
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din_rev[i] = right_nleft ? din[W_DATA - 1 - i] : din[i];
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sext = arith && din_rev[0];
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shift_accum = din_rev;
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for (i = 0; i < W_SHAMT; i = i + 1) begin
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if (shamt[i]) begin
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shift_accum = (shift_accum << (1 << i)) |
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({W_DATA{sext}} & ~({W_DATA{1'b1}} << (1 << i))) |
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({W_DATA{rotate && |EXTENSION_ZBB}} & (shift_accum >> (W_DATA - (1 << i))));
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end
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end
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for (i = 0; i < W_DATA; i = i + 1)
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dout[i] = right_nleft ? shift_accum[W_DATA - 1 - i] : shift_accum[i];
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end
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`ifdef HAZARD3_ASSERTIONS
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always @ (*) begin
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if (right_nleft && arith && !rotate) begin: asr
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assert($signed(dout) == $signed(din) >>> $signed(shamt));
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end else if (right_nleft && !arith && !rotate) begin
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assert(dout == din >> shamt);
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end else if (!right_nleft && !arith && !rotate) begin
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assert(dout == din << shamt);
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end
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end
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`endif
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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