Hazard3/test/sim/common
Luke Wren ad5fd24772 - Fix signal named priority, which is a keyword in SV
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
  the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
..
hazard3_csr.h Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-07 22:04:42 +01:00
hazard3_irq.h Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-07 22:04:42 +01:00
init.S Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00
irq_dispatch.S - Fix signal named priority, which is a keyword in SV 2022-08-07 23:17:03 +01:00
memmap.ld Add RISC-V debug tests 2021-07-22 17:50:04 +01:00
src_only_app.mk Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb_cxxrtl_io.h Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00