Luke Wren 5193dfe477 Add separate define HAZARD3_ASSERTIONS for enabling internal assertions, ... and enable it only on the bus compliance model checks. Trying to make the solver's life easier in instruction_fetch_match.		2022-06-25 20:08:40 +01:00
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bus_compliance_1port	Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,	2022-06-25 20:08:40 +01:00
bus_compliance_2port	Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,	2022-06-25 20:08:40 +01:00
common	Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.	2021-12-18 15:41:05 +00:00
frontend_fetch_match	First pass at adding branch prediction	2022-06-15 02:05:46 +01:00
instruction_fetch_match	Fix some bugs, too tired to list them, look at the diff	2022-06-15 04:05:31 +01:00
riscv-formal	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
.gitignore	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00