47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Really something like this should be in a utility library (or the language!),
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// but Hazard3 is supposed to be self-contained
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`default_nettype none
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module hazard3_priority_encode #(
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parameter W_REQ = 16,
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parameter W_GNT = $clog2(W_REQ) // do not modify
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) (
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input wire [W_REQ-1:0] req,
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output wire [W_GNT-1:0] gnt
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);
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// First do a priority-select of the input bitmap.
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reg [W_REQ-1:0] gnt_onehot;
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always @ (*) begin: smear
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integer i;
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for (i = 0; i < W_REQ; i = i + 1)
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gnt_onehot[i] = req[i] && ~|(req & ~({W_REQ{1'b1}} << i));
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end
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// As the result is onehot, we can now just OR in the representation of each
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// encoded integer.
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reg [W_GNT-1:0] gnt_accum;
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always @ (*) begin: encode
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reg [W_GNT:0] i;
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gnt_accum = {W_GNT{1'b0}};
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for (i = 0; i < W_REQ; i = i + 1) begin
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gnt_accum = gnt_accum | ({W_GNT{gnt_onehot[i]}} & i[W_GNT-1:0]);
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end
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end
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assign gnt = gnt_accum;
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endmodule
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`default_nettype wire
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