History

Luke Wren 35c5e213c7 Bump embench for working benchmarks (except md5)		2021-11-29 00:59:14 +00:00
..
embench-iot@bd42227cd1	Bump embench for working benchmarks (except md5)	2021-11-29 00:59:14 +00:00
Readme.md	Add embench submodule, with configs for hazard3	2021-11-28 00:01:18 +00:00

Readme.md

Embench

To run these benchmarks, first make sure the embench-iot submodule is checked out, then:

cd embench-iot
# Make sure testbench is up to date
make -C ../../tb_cxxrtl tb
./build_all.py --arch riscv32 --chip hazard3 --board hazard3tb
./benchmark_speed --target-module run_hazard3tb

The compiler specified in config/riscv32/chips/hazard3/chip.cfg is /opt/riscv/unstable/bin/riscv32-unknown-elf-gcc, which is where I have an unstable GCC 12 build installed on my machine. You need to have a recent upstream master build to support the Zba/Zbb/Zbc/Zbs instructions. If you don't care about these, you can use whatever riscv32-unknown-elf compiler you have, and also edit cflags in that .cfg file to not include the bitmanip extensions in march.