Hazard3/example_soc/soc
Luke Wren 15cb21ae43 First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
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example_soc.v First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
soc.f Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address. 2022-06-13 01:23:32 +01:00