75 lines
2.0 KiB
Verilog
75 lines
2.0 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Standalone bus shim for connecting the DM's System Bus Access to AHB
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`default_nettype none
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module hazard3_sbus_to_ahb #(
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parameter W_ADDR = 32,
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parameter W_DATA = 32
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) (
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input wire clk,
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input wire rst_n,
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input wire [W_ADDR-1:0] sbus_addr,
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input wire sbus_write,
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input wire [1:0] sbus_size,
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input wire sbus_vld,
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output wire sbus_rdy,
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output wire sbus_err,
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input wire [W_DATA-1:0] sbus_wdata,
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output wire [W_DATA-1:0] sbus_rdata,
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output wire [W_ADDR-1:0] ahblm_haddr,
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output wire ahblm_hwrite,
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output wire [1:0] ahblm_htrans,
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output wire [2:0] ahblm_hsize,
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output wire [2:0] ahblm_hburst,
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output wire [3:0] ahblm_hprot,
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output wire ahblm_hmastlock,
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input wire ahblm_hready,
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input wire ahblm_hresp,
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output wire [W_DATA-1:0] ahblm_hwdata,
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input wire [W_DATA-1:0] ahblm_hrdata
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);
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// Most signals are simple tie-throughs
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assign ahblm_haddr = sbus_addr;
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assign ahblm_hwrite = sbus_write;
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assign ahblm_hsize = {1'b0, sbus_size};
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assign ahblm_hwdata = sbus_wdata;
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// HPROT = noncacheable nonbufferable privileged data access:
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assign ahblm_hprot = 4'b0011;
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assign ahblm_hmastlock = 1'b0;
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assign ahblm_hburst = 3'h0;
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assign sbus_err = ahblm_hresp;
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assign sbus_rdata = ahblm_hrdata;
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// Handshaking
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reg dph_active;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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dph_active <= 1'b0;
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end else if (ahblm_hready) begin
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dph_active <= ahblm_htrans[1];
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end
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end
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assign ahblm_htrans = sbus_vld && !dph_active ? 2'b10 : 2'b00;
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assign sbus_rdy = ahblm_hready && dph_active;
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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