c81666177e
in calculating the privilege of load/stores. This is safe because it is only the *current* debug mode state which affects load/stores, and some new properties have been added to ensure load/stores can not be in aphase at the point debug mode is entered/exited (which is achieved by delaying the trap). Therefore there is no way for debug entry to inadvertently boost the privilege of an executing U-mode load/store. Also rename a confusingly-named signal for an unsquashable bus transfer in stage 2 that delays IRQ entry. |
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| .. | ||
| arith | ||
| debug | ||
| hazard3.f | ||
| hazard3_config.vh | ||
| hazard3_config_inst.vh | ||
| hazard3_core.v | ||
| hazard3_cpu_1port.v | ||
| hazard3_cpu_2port.v | ||
| hazard3_csr.v | ||
| hazard3_csr_addr.vh | ||
| hazard3_decode.v | ||
| hazard3_frontend.v | ||
| hazard3_instr_decompress.v | ||
| hazard3_irq_ctrl.v | ||
| hazard3_ops.vh | ||
| hazard3_pmp.v | ||
| hazard3_power_ctrl.v | ||
| hazard3_regfile_1w2r.v | ||
| hazard3_triggers.v | ||
| hazard3_width_const.vh | ||
| rv_opcodes.vh | ||