Luke Wren 8721bd3deb Add RISC-V timer to example soc, and tweak ULX3S config		2022-10-07 03:11:36 +01:00
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fpga	Add RISC-V timer to example soc, and tweak ULX3S config	2022-10-07 03:11:36 +01:00
libfpga@9d50e12e01	Bump libfpga for correct bus error response from AHBL splitter in example SoC	2021-11-28 01:35:52 +00:00
soc	Add RISC-V timer to example soc, and tweak ULX3S config	2022-10-07 03:11:36 +01:00
synth	Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker	2021-11-21 15:55:52 +00:00
icebreaker-openocd.cfg	Small code cleanup	2021-07-24 10:08:27 +01:00
ulx3s-openocd.cfg	Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.	2021-07-23 18:32:47 +01:00