53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Properties for driving the debug module system bus access patch-through
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// core interface in the bus property checks
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`default_nettype none
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module sbus_assumptions #(
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parameter W_ADDR = 32,
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parameter W_DATA = 32
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) (
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input wire clk,
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input wire rst_n,
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input wire [W_ADDR-1:0] dbg_sbus_addr,
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input wire dbg_sbus_write,
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input wire [1:0] dbg_sbus_size,
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input wire dbg_sbus_vld,
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input wire dbg_sbus_rdy,
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input wire dbg_sbus_err,
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input wire [W_DATA-1:0] dbg_sbus_wdata,
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input wire [W_DATA-1:0] dbg_sbus_rdata
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);
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// Naturally aligned, no larger than bus
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always assume(~|(dbg_sbus_addr & ~({32{1'b1}} << dbg_sbus_size)));
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always assume(dbg_sbus_size < 2'h3);
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// No transfers whilst core is in reset
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always assume(!(!rst_n && dbg_sbus_vld));
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// No change or retraction of active transfer
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always @ (posedge clk) if (rst_n) begin
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if ($past(dbg_sbus_vld && !dbg_sbus_rdy)) begin
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assume($stable({
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dbg_sbus_vld,
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dbg_sbus_addr,
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dbg_sbus_size,
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dbg_sbus_write,
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dbg_sbus_wdata
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}));
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end
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end
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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