Luke Wren 1953773ca5 Don't gate exception into D-mode CSR write, as a valid CSR instruction ... writing to a valid CSR in D-mode is guaranteed not to raise any exception (particularly the external data0 CSR is of interest)		2022-10-10 22:15:56 +01:00
..
arith	Remove op_b (rs2) register from muldiv_seq for modest LUT/FF savings	2022-10-08 18:22:16 +01:00
debug	Fix bad preprocessor conditional in ECP5 JTAG DTM	2022-09-04 23:48:58 +01:00
hazard3.f	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_config.vh	Don't reset register file by default	2022-10-08 16:24:28 +01:00
hazard3_config_inst.vh	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_core.v	Don't gate exception into D-mode CSR write, as a valid CSR instruction	2022-10-10 22:15:56 +01:00
hazard3_cpu_1port.v	First stab at adding wake/sleep state machine	2022-08-28 19:50:04 +01:00
hazard3_cpu_2port.v	First stab at adding wake/sleep state machine	2022-08-28 19:50:04 +01:00
hazard3_csr.v	Don't gate exception into D-mode CSR write, as a valid CSR instruction	2022-10-10 22:15:56 +01:00
hazard3_csr_addr.vh	First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.	2022-08-22 08:47:03 +01:00
hazard3_decode.v	Alias DPC to the real program counter, small savings overall	2022-10-10 00:28:42 +01:00
hazard3_frontend.v	Arrange for address buses to be 0 when processor is held in reset	2022-10-08 16:50:58 +01:00
hazard3_instr_decompress.v	Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation	2022-08-20 16:22:04 +01:00
hazard3_irq_ctrl.v	Tidy up priority tie-offs in irq_ctrl	2022-10-08 16:25:05 +01:00
hazard3_ops.vh	Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains	2022-08-06 23:02:08 +01:00
hazard3_pmp.v	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_power_ctrl.v	Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.	2022-08-29 19:20:09 +01:00
hazard3_regfile_1w2r.v	Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression	2022-09-04 23:56:14 +01:00
hazard3_triggers.v	Doh	2022-09-08 15:11:24 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	Fix some whitespace issues, and avoid redefinition of RVOPC macros	2022-08-21 13:09:28 +01:00