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Hazard3/test/sim/riscv-tests
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Luke Wren e44d2e6f9e Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed 2022-07-03 23:34:12 +01:00
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riscv-tests@0211e0dacc Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed 2022-07-03 23:34:12 +01:00
debug.gtkw Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed 2022-07-03 23:34:12 +01:00
run-debug-tests.sh Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed 2022-07-03 23:34:12 +01:00
run-isa-tests.sh Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented. 2022-05-28 17:22:28 +01:00
run-smp-debug-tests.sh Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed 2022-07-03 23:34:12 +01:00