Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.		2022-06-13 01:23:32 +01:00
..
arith	Update copyright years	2022-06-09 00:12:01 +01:00
debug	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3.f	Integrate PMP, and fix a couple of PMP bugs	2022-05-24 19:57:45 +01:00
hazard3_config.vh	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_config_inst.vh	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_core.v	Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush	2022-06-12 21:01:39 +01:00
hazard3_cpu_1port.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_cpu_2port.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_csr.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_csr_addr.vh	First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.	2022-05-24 16:17:54 +01:00
hazard3_decode.v	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
hazard3_frontend.v	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
hazard3_instr_decompress.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_ops.vh	ecall from U-mode has a different mcause value than ecall from M-mode	2022-05-28 12:07:29 +01:00
hazard3_pmp.v	PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.	2022-06-03 17:09:43 +01:00
hazard3_regfile_1w2r.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	Correct the name and operation of the brev8 (formerly rev.b) instruction	2022-05-20 15:28:18 +01:00