Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.		2022-06-13 01:23:32 +01:00
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formal	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
sim	Make rvpy cycle-accurate enough to get the correct Dhrystone score	2022-06-09 01:34:37 +01:00
.gitignore	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00