(i.e. single-core testbench). Avoids some odd behaviour with wide assignment to single-bit wire from the CXXRTL harness. |
||
---|---|---|
.. | ||
formal | ||
sim | ||
.gitignore |
(i.e. single-core testbench). Avoids some odd behaviour with wide assignment to single-bit wire from the CXXRTL harness. |
||
---|---|---|
.. | ||
formal | ||
sim | ||
.gitignore |