40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// The output is asserted asynchronously when the input is asserted,
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// but deasserted synchronously when clocked with the input deasserted.
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// Input and output are both active-low.
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//
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// This is a baseline implementation -- you should replace it with cells
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// specific to your FPGA/process
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`ifndef HAZARD3_REG_KEEP_ATTRIBUTE
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`define HAZARD3_REG_KEEP_ATTRIBUTE (* keep = 1'b1 *)
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`endif
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`default_nettype none
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module hazard3_reset_sync #(
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parameter N_STAGES = 2 // Should be >= 2
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) (
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input wire clk,
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input wire rst_n_in,
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output wire rst_n_out
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);
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`HAZARD3_REG_KEEP_ATTRIBUTE reg [N_STAGES-1:0] delay;
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always @ (posedge clk or negedge rst_n_in)
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if (!rst_n_in)
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delay <= {N_STAGES{1'b0}};
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else
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delay <= {delay[N_STAGES-2:0], 1'b1};
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assign rst_n_out = delay[N_STAGES-1];
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endmodule
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`default_nettype wire
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