38 lines
1011 B
Verilog
38 lines
1011 B
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// A 2FF synchronizer to mitigate metastabilities. This is a baseline
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// implementation -- you should replace it with cells specific to your
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// FPGA/process
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`ifndef HAZARD3_REG_KEEP_ATTRIBUTE
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`define HAZARD3_REG_KEEP_ATTRIBUTE (* keep = 1'b1 *)
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`endif
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`default_nettype none
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module hazard3_sync_1bit #(
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parameter N_STAGES = 2 // Should be >=2
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) (
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input wire clk,
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input wire rst_n,
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input wire i,
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output wire o
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);
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`HAZARD3_REG_KEEP_ATTRIBUTE reg [N_STAGES-1:0] sync_flops;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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sync_flops <= {N_STAGES{1'b0}};
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else
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sync_flops <= {sync_flops[N_STAGES-2:0], i};
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assign o = sync_flops[N_STAGES-1];
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endmodule
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`default_nettype wire
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