99 lines
3.0 KiB
Verilog
99 lines
3.0 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2018 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// Register file
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// Single write port, dual read port
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// FAKE_DUALPORT: if 1, implement regfile with pair of memories.
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// Write ports are ganged together, read ports operate independently.
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// This allows BRAM inference on FPGAs with single-read-port BRAMs.
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// (Looking at you iCE40)
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`default_nettype none
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module hazard3_regfile_1w2r #(
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parameter FAKE_DUALPORT = 0,
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parameter RESET_REGS = 0, // Unsupported for FAKE_DUALPORT
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parameter N_REGS = 16,
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parameter W_DATA = 32,
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parameter W_ADDR = $clog2(W_DATA) // should be localparam. ISIM...
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) (
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input wire clk,
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input wire rst_n,
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input wire [W_ADDR-1:0] raddr1,
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output reg [W_DATA-1:0] rdata1,
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input wire [W_ADDR-1:0] raddr2,
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output reg [W_DATA-1:0] rdata2,
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input wire [W_ADDR-1:0] waddr,
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input wire [W_DATA-1:0] wdata,
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input wire wen
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);
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generate
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if (FAKE_DUALPORT) begin: fake_dualport
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reg [W_DATA-1:0] mem1 [0:N_REGS-1];
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reg [W_DATA-1:0] mem2 [0:N_REGS-1];
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always @ (posedge clk) begin
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if (wen) begin
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mem1[waddr] <= wdata;
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mem2[waddr] <= wdata;
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end
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rdata1 <= mem1[raddr1];
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rdata2 <= mem2[raddr2];
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end
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end else if (RESET_REGS) begin: real_dualport_reset
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// This will presumably always be implemented with flops
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reg [W_DATA-1:0] mem [0:N_REGS-1];
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integer i;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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for (i = 0; i < N_REGS; i = i + 1) begin
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mem[i] <= {W_DATA{1'b0}};
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end
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rdata1 <= {W_DATA{1'b0}};
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rdata2 <= {W_DATA{1'b0}};
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end else begin
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if (wen) begin
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mem[waddr] <= wdata;
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end
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rdata1 <= mem[raddr1];
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rdata2 <= mem[raddr2];
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end
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end
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end else begin: real_dualport_noreset
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// This should be inference-compatible on FPGAs with dual-port BRAMs
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reg [W_DATA-1:0] mem [0:N_REGS-1];
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always @ (posedge clk) begin
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if (wen) begin
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mem[waddr] <= wdata;
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end
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rdata1 <= mem[raddr1];
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rdata2 <= mem[raddr2];
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end
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end
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endgenerate
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endmodule
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`default_nettype wire
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