207 lines
6.6 KiB
Verilog
207 lines
6.6 KiB
Verilog
// This is not really a "testbench", just an integration of CPU + DM for a
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// CXXRTL test to poke at
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module tb #(
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parameter W_DATA = 32,
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parameter W_ADDR = 32,
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parameter NUM_IRQ = 16
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) (
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// Global signals
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input wire clk,
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input wire rst_n,
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// Instruction fetch port
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output wire [W_ADDR-1:0] i_haddr,
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output wire i_hwrite,
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output wire [1:0] i_htrans,
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output wire [2:0] i_hsize,
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output wire [2:0] i_hburst,
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output wire [3:0] i_hprot,
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output wire i_hmastlock,
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input wire i_hready,
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input wire i_hresp,
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output wire [W_DATA-1:0] i_hwdata,
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input wire [W_DATA-1:0] i_hrdata,
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// Load/store port
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output wire [W_ADDR-1:0] d_haddr,
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output wire d_hwrite,
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output wire [1:0] d_htrans,
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output wire [2:0] d_hsize,
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output wire [2:0] d_hburst,
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output wire [3:0] d_hprot,
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output wire d_hmastlock,
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input wire d_hready,
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input wire d_hresp,
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output wire [W_DATA-1:0] d_hwdata,
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input wire [W_DATA-1:0] d_hrdata,
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// Debug module interface
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input wire dmi_psel,
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input wire dmi_penable,
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input wire dmi_pwrite,
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input wire [7:0] dmi_paddr,
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input wire [31:0] dmi_pwdata,
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output reg [31:0] dmi_prdata,
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output wire dmi_pready,
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output wire dmi_pslverr,
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// Level-sensitive interrupt sources
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input wire [NUM_IRQ-1:0] irq, // -> mip.meip
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input wire soft_irq, // -> mip.msip
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input wire timer_irq // -> mip.mtip
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);
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localparam N_HARTS = 1;
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localparam XLEN = 32;
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wire sys_reset_req;
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wire sys_reset_done;
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wire [N_HARTS-1:0] hart_reset_req;
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wire [N_HARTS-1:0] hart_reset_done;
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wire [N_HARTS-1:0] hart_req_halt;
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wire [N_HARTS-1:0] hart_req_halt_on_reset;
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wire [N_HARTS-1:0] hart_req_resume;
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wire [N_HARTS-1:0] hart_halted;
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wire [N_HARTS-1:0] hart_running;
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wire [N_HARTS*XLEN-1:0] hart_data0_rdata;
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wire [N_HARTS*XLEN-1:0] hart_data0_wdata;
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wire [N_HARTS-1:0] hart_data0_wen;
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wire [N_HARTS*XLEN-1:0] hart_instr_data;
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wire [N_HARTS-1:0] hart_instr_data_vld;
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wire [N_HARTS-1:0] hart_instr_data_rdy;
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wire [N_HARTS-1:0] hart_instr_caught_exception;
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wire [N_HARTS-1:0] hart_instr_caught_ebreak;
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hazard3_dm #(
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.N_HARTS (N_HARTS),
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.NEXT_DM_ADDR (0)
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) dm (
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.clk (clk),
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.rst_n (rst_n),
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.dmi_psel (dmi_psel),
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.dmi_penable (dmi_penable),
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.dmi_pwrite (dmi_pwrite),
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.dmi_paddr (dmi_paddr),
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.dmi_pwdata (dmi_pwdata),
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.dmi_prdata (dmi_prdata),
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.dmi_pready (dmi_pready),
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.dmi_pslverr (dmi_pslverr),
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.sys_reset_req (sys_reset_req),
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.sys_reset_done (sys_reset_done),
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.hart_reset_req (hart_reset_req),
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.hart_reset_done (hart_reset_done),
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.hart_req_halt (hart_req_halt),
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.hart_req_halt_on_reset (hart_req_halt_on_reset),
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.hart_req_resume (hart_req_resume),
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.hart_halted (hart_halted),
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.hart_running (hart_running),
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.hart_data0_rdata (hart_data0_rdata),
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.hart_data0_wdata (hart_data0_wdata),
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.hart_data0_wen (hart_data0_wen),
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.hart_instr_data (hart_instr_data),
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.hart_instr_data_vld (hart_instr_data_vld),
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.hart_instr_data_rdy (hart_instr_data_rdy),
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.hart_instr_caught_exception (hart_instr_caught_exception),
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.hart_instr_caught_ebreak (hart_instr_caught_ebreak)
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);
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// Generate resynchronised reset for CPU based on upstream reset and
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// on reset requests from DM.
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wire assert_cpu_reset = !rst_n || sys_reset_req || hart_reset_req[0];
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reg [1:0] cpu_reset_sync;
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wire rst_n_cpu = cpu_reset_sync[1];
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always @ (posedge clk or posedge assert_cpu_reset)
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if (assert_cpu_reset)
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cpu_reset_sync <= 2'b00;
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else
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cpu_reset_sync <= (cpu_reset_sync << 1) | 2'b01;
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// Still some work to be done on the reset handshake -- this ought to be
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// resynchronised to DM's reset domain here, and the DM should wait for a
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// rising edge after it has asserted the reset pulse, to make sure the tail
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// of the previous "done" is not passed on.
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assign sys_reset_done = rst_n_cpu;
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assign hart_reset_done = rst_n_cpu;
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hazard3_cpu_2port #(
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.RESET_VECTOR (32'hc0),
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.MTVEC_INIT (32'h00),
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.EXTENSION_C (1),
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.EXTENSION_M (1),
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.CSR_M_MANDATORY (1),
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.CSR_M_TRAP (1),
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.CSR_COUNTER (1),
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.DEBUG_SUPPORT (1),
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.NUM_IRQ (NUM_IRQ),
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.MVENDORID_VAL (32'hdeadbeef),
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.MARCHID_VAL (32'hfeedf00d),
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.MIMPID_VAL (32'h12345678),
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.MHARTID_VAL (32'h0),
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.REDUCED_BYPASS (0),
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.MULDIV_UNROLL (2),
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.MUL_FAST (1),
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) cpu (
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.clk (clk),
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.rst_n (rst_n_cpu),
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.i_haddr (i_haddr),
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.i_hwrite (i_hwrite),
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.i_htrans (i_htrans),
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.i_hsize (i_hsize),
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.i_hburst (i_hburst),
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.i_hprot (i_hprot),
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.i_hmastlock (i_hmastlock),
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.i_hready (i_hready),
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.i_hresp (i_hresp),
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.i_hwdata (i_hwdata),
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.i_hrdata (i_hrdata),
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.d_haddr (d_haddr),
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.d_hwrite (d_hwrite),
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.d_htrans (d_htrans),
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.d_hsize (d_hsize),
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.d_hburst (d_hburst),
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.d_hprot (d_hprot),
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.d_hmastlock (d_hmastlock),
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.d_hready (d_hready),
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.d_hresp (d_hresp),
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.d_hwdata (d_hwdata),
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.d_hrdata (d_hrdata),
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.dbg_req_halt (hart_req_halt),
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.dbg_req_halt_on_reset (hart_req_halt_on_reset),
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.dbg_req_resume (hart_req_resume),
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.dbg_halted (hart_halted),
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.dbg_running (hart_running),
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.dbg_data0_rdata (hart_data0_rdata),
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.dbg_data0_wdata (hart_data0_wdata),
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.dbg_data0_wen (hart_data0_wen),
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.dbg_instr_data (hart_instr_data),
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.dbg_instr_data_vld (hart_instr_data_vld),
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.dbg_instr_data_rdy (hart_instr_data_rdy),
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.dbg_instr_caught_exception (hart_instr_caught_exception),
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.dbg_instr_caught_ebreak (hart_instr_caught_ebreak),
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.irq (irq),
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.soft_irq (soft_irq),
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.timer_irq (timer_irq)
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);
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endmodule
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