65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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/*EXPECTED-OUTPUT***************************************************************
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Dry run
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Set mie only
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Then set IRQ
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-> handle_soft_irq
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mip = 00000088 // mtip is also set, because mtimecmp is 0
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mie = 00000008 // only msie is set
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mcause = 80000003 // MSB indicates IRQ. LSBs are index of mip.
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mstatus = 00001880 // MPP = 3. mpie = 1, mie = 0, since we just took an IRQ.
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Returned from IRQ
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Clear mie, do another dry run
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*******************************************************************************/
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#define mip_msip 0x8u
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#define mie_msie mip_msip
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int main() {
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tb_assert(!(read_csr(mip) & mip_msip), "mip.msip should be clear at start of test\n");
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tb_puts("Dry run\n");
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tb_set_softirq(0);
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tb_assert(tb_get_softirq(0), "Failed to set soft_irq through tb\n");
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tb_assert(read_csr(mip) & mip_msip, "soft_irq not reflected in mip\n");
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tb_clr_softirq(0);
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tb_assert(!tb_get_softirq(0), "Failed to clear soft_irq through tb\n");
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tb_assert(!(read_csr(mip) & mip_msip), "soft_irq clear not reflected in mip\n");
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tb_puts("Set mie only\n");
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write_csr(mie, mie_msie);
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asm volatile ("csrsi mstatus, 0x8");
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// IRQ should not fire yet.
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tb_puts("Then set IRQ\n");
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tb_set_softirq(0);
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tb_assert(!(read_csr(mip) & mip_msip), "soft_irq should have been cleared by IRQ\n");
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tb_puts("Returned from IRQ\n");
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tb_puts("Clear mie, do another dry run\n");
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write_csr(mie, 0);
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tb_set_softirq(0);
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tb_assert(tb_get_softirq(0), "Failed to set soft_irq through tb\n");
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tb_assert(read_csr(mip) & mip_msip, "soft_irq not reflected in mip\n");
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tb_clr_softirq(0);
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tb_assert(!tb_get_softirq(0), "Failed to clear soft_irq through tb\n");
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tb_assert(!(read_csr(mip) & mip_msip), "soft_irq clear not reflected in mip\n");
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return 0;
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}
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void __attribute__((interrupt)) isr_machine_softirq() {
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tb_puts("-> handle_soft_irq\n");
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tb_printf("mip = %08x\n", read_csr(mip));
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tb_printf("mie = %08x\n", read_csr(mie));
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tb_clr_softirq(0);
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tb_printf("mcause = %08x\n", read_csr(mcause));
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tb_printf("mstatus = %08x\n", read_csr(mstatus));
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}
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