Enable demo of jtag.

demo/.gitignore

@@ -0,0 +1,3 @@
+build/
+obj_dir/
+gen/

demo/Makefile

@@ -1,13 +1,14 @@
-export RV_ROOT = ${PWD}/../..
+export RV_ROOT = ${PWD}/..
+GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
 GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
 
-
-TEST_CFLAGS = -g -O3 -funroll-all-loops
 ABI = -mabi=ilp32 -march=rv32imc
 
 DEMODIR = ${PWD}
 BUILD_DIR = ${DEMODIR}/build
-RV_SOC = ${RV_ROOT}/quasar
+DEFINE_DIR = ${DEMODIR}/../design/snapshots/default
+
+RV_SOC = ${RV_ROOT}/soc
 
 TEST = jtag
 
@@ -17,6 +18,7 @@ ifdef debug
 endif
 
 LINK = $(DEMODIR)/link.ld
+LINKPRO = $(DEMODIR)/link_pro.ld
 
 # CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
 CFLAGS += "-std=c++11"
@@ -30,38 +32,45 @@ all: clean verilator
 clean:
 	rm -rf build obj_dir
 
-swerv_define :
-	BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
-
 ##################### Verilog Builds #####################################
 
-verilator-build: swerv_define
-	echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
+verilator-build:
+	echo '`undef RV_ASSERT_ON' >> ${DEFINE_DIR}/common_defines.vh
 	verilator --cc -CFLAGS ${CFLAGS} \
-	              $(BUILD_DIR)/common_defines.vh \
-	              -I${BUILD_DIR} \
-	              -Wno-UNOPTFLAT \
+	              $(DEFINE_DIR)/common_defines.vh \
+	              -I${DEFINE_DIR} \
 								-Wno-WIDTH \
+	              -Wno-UNOPTFLAT \
 								-Wno-LATCH \
-								-Wno-IMPLICIT \
 	              -F ${RV_SOC}/soc_top.mk \
 	              -F ${RV_SOC}/soc_sim.mk \
 	              $(RV_SOC)/soc_sim.sv \
 	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
 	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
-	$(MAKE) -j -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
+	$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
 
 ##################### Simulation Runs #####################################
 
-verilator: program verilator-build
+verilator: program.hex verilator-build
+	cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
+
+sim:
 	cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
 
 ##################### Test hex Build #####################################
 
-program:
-	@mkdir build
-	@cp program.hex build/program.hex
-	@cp jtag.bin build/jtag.bin
+program.hex: $(TEST).o $(LINK)
+	@echo Building $(TEST)
+	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINKPRO) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
+	$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
+	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
+	$(GCC_PREFIX)-objdump -S  $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
+	@echo Completed building $(TEST)
+
+%.o : %.s
+	@mkdir -p $(BUILD_DIR)
+	$(GCC_PREFIX)-cpp -g -I${DEFINE_DIR}  $<  > $(BUILD_DIR)/$*.cpp.s
+	$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
 
 ##################### openocd #####################################
 

demo/gdbinit

@@ -1,3 +1,3 @@
 # set debug remote 1
-target remote :3333
+target extended-remote :3333
 set remotetimeout 2000

demo/jtag.s

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// Assembly code for Hello World
+// Not using only ALU ops for creating the string
+
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+    // Clear minstret
+    csrw minstret, zero
+    csrw minstreth, zero
+
+    // Set up MTVEC - not expecting to use it though
+    li x1, RV_ICCM_SADR
+    csrw mtvec, x1
+
+
+    // Enable Caches in MRAC
+    li x1, 0x5f555555
+    csrw 0x7c0, x1
+
+    // Load string from hw_data
+    // and write to stdout address
+
+    li x3, STDOUT
+    la x4, hw_data
+
+loop:
+   lb x5, 0(x4)
+   sb x5, 0(x3)
+   addi x4, x4, 1
+   bnez x5, loop
+
+   li x3, STDOUT
+   la x4, hw_data
+
+loop2:
+   lb x5, 0(x4)
+   sb x5, 0(x3)
+   addi x4, x4, 1
+   bnez x5, loop2
+
+loop3:
+   beq x0, x0, loop3
+
+// Write 0xff to STDOUT for TB to terminate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+
+.global hw_data
+.data
+hw_data:
+.ascii "----------------------------------\n"
+.ascii "Hello World Colin.liang EL2@WDC !!\n"
+.ascii "----------------------------------\n"
+.byte 0

demo/link.ld

@@ -0,0 +1,16 @@
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text_init   : { *(.text_init*) }
+  .text   : { *(.text*) }
+  _end = .;
+  . = 0x80004000;
+  .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
+  .bss : { *(.bss) }
+  . = 0xd0580000;
+  .data.io   : { *(.data.io) }
+}

demo/link_pro.ld

@@ -0,0 +1,16 @@
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x0000;
+  .text_init   : { *(.text_init*) }
+  .text   : { *(.text*) }
+  _end = .;
+  . = 0x4000;
+  .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
+  .bss : { *(.bss) }
+  . = 0xd0580000;
+  .data.io   : { *(.data.io) }
+}

demo/program.hex

@@ -1,28 +0,0 @@
-@00000000
-73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
-B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
-17 42 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
-05 02 E3 9B 02 FE B7 01 58 D0 17 42 00 00 13 02
-62 FC 83 02 02 00 23 80 51 00 05 02 E3 9B 02 FE
-63 00 00 00 B7 01 58 D0 93 02 F0 0F 23 80 51 00
-E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
-01 00 01 00 01 00 01 00 01 00 01 00
-@00004000
-2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
-2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
-2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 43
-6F 6C 69 6E 2E 6C 69 61 6E 67 20 45 4C 32 40 57
-44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
-2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
-2D 2D 2D 2D 2D 2D 2D 2D 0A 00

demo/soc.lpf

@@ -0,0 +1,32 @@
+LOCATE COMP "clk" SITE "P3";
+IOBUF PORT "clk" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 25 MHZ;
+
+LOCATE COMP "dbg_rst" SITE "N2";
+IOBUF PORT "dbg_rst" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "dbg_rst" 25 MHZ;
+
+LOCATE COMP "rst" SITE "N3";
+IOBUF PORT "rst" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "rst" 25 MHZ;
+
+LOCATE COMP "jtag_tck" SITE "T2";
+IOBUF PORT "jtag_tck" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_tck" 25 MHZ;
+
+LOCATE COMP "jtag_tms" SITE "T3";
+IOBUF PORT "jtag_tms" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_tms" 25 MHZ;
+
+LOCATE COMP "jtag_tdi" SITE "N4";
+IOBUF PORT "jtag_tdi" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_tdi" 25 MHZ;
+
+LOCATE COMP "jtag_trst_n" SITE "M3";
+IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_trst_n" 25 MHZ;
+
+
+
+LOCATE COMP "jtag_tdo" SITE "M4";
+IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;

demo/synth.sh

@@ -0,0 +1,83 @@
+#!/bin/bash
+
+# if [ $# -ne 1 -o ! -d "$1" ]; then
+# 	echo "Usage: $0 <design>" >&2
+# 	exit 1
+# fi
+
+set -ex
+
+PWD=$(pwd)
+SOC=$PWD/../../soc
+design=${1%/}
+
+YOSYS_COARSE=true
+YOSYS_GLOBRST=false
+YOSYS_SPLITNETS=false
+TOP="soc_top"
+RTL=$(cat ../../soc/soc_top.mk)
+
+rtl_files=""
+
+rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
+rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
+rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
+# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
+# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
+
+for src in $RTL; do
+	rtl_files="$rtl_files $SOC/$src"
+done
+
+mkdir -p gen
+rm -rf gen/*
+mkdir gen/design
+
+
+filelist=""
+for file in $rtl_files; do
+	filelist="$filelist $file"
+done
+# sv2v $filelist > gen/soc_top.v
+sv2v -Ibuild $filelist > gen/soc_top.v
+
+{
+	# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
+  # for file in $rtl_files; do
+	# 	echo "read_verilog -sv -I../../design/include $file"
+	# done
+	echo "read_verilog gen/soc_top.v"
+
+	if test -n "$TOP"; then
+		echo "hierarchy -check -top $TOP"
+	else
+		echo "hierarchy -check"
+	fi
+	if $YOSYS_GLOBRST; then
+		# insertation of global reset (e.g. for FPGA cores)
+		echo "add -global_input globrst 1"
+		echo "proc -global_arst globrst"
+	fi
+	echo "synth -run coarse; opt -fine"
+	# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
+	if ! $YOSYS_COARSE; then
+		echo "memory_map; techmap; opt; abc -dff; clean"
+	fi
+	if $YOSYS_SPLITNETS; then
+		# icarus verilog has a performance problems when there are
+		# dependencies between the bits of a long vector
+		echo "splitnets; clean"
+	fi
+	if $YOSYS_COARSE; then
+		echo "write_verilog -noexpr -noattr gen/synth.v"
+	else
+		echo "select -assert-none t:\$[!_]"
+		echo "write_verilog -noattr gen/synth.v"
+	fi
+	echo "synth_ecp5 -top $TOP -json gen/soc.json"
+	# echo "synth_xilinx -top $TOP"
+} > gen/synth.ys
+
+yosys -v2 -l gen/synth.log gen/synth.ys
+
+nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1  --json gen/soc.json

soc/dpi/jtagdpi/jtagdpi.sv

@@ -17,16 +17,22 @@ module jtagdpi #(
     output logic jtag_srst_n
 );
 
-  import "DPI-C"
-  function chandle jtagdpi_create(input string name, input int listen_port);
+  import "DPI-C" function chandle jtagdpi_create(
+    input string name,
+    input int listen_port
+  );
 
-  import "DPI-C"
-  function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms,
-                             output bit tdi, output bit trst_n,
-                             output bit srst_n, input bit tdo);
+  import "DPI-C" function void jtagdpi_tick(
+    input chandle ctx,
+    output bit tck,
+    output bit tms,
+    output bit tdi,
+    output bit trst_n,
+    output bit srst_n,
+    input bit tdo
+  );
 
-  import "DPI-C"
-  function void jtagdpi_close(input chandle ctx);
+  import "DPI-C" function void jtagdpi_close(input chandle ctx);
 
   chandle ctx;
 
@@ -39,7 +45,10 @@ module jtagdpi #(
     ctx = 0;
   end
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  reg [1:0] plit;
+  always_ff @(posedge clk_i) plit <= plit + 1'b1;
+
+  always_ff @(posedge plit[1], negedge rst_ni) begin
     jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
                  jtag_tdo);
   end

soc/soc_sim.sv

@@ -1,19 +1,3 @@
-// SPDX-License-Identifier: Apache-2.0
-// Copyright 2020 Western Digital Corporation or its affiliates.
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-
 module soc_sim (
     input bit core_clk
 );
@@ -343,6 +327,9 @@ module soc_sim (
     abi_reg[30] = "t5";
     abi_reg[31] = "t6";
 
+    $readmemh("program.hex", rvsoc.lmem.mem);
+    $readmemh("program.hex", rvsoc.imem.mem);
+
     tp  = $fopen("trace_port.csv", "w");
     el  = $fopen("exec.log", "w");
     //////////////////////////////////////////////////////////////////

soc/soc_top.mk

@@ -1,15 +1,15 @@
-./quasar_wrapper.sv
+../generated_rtl/quasar_wrapper.sv
 
-vsrc/mem.sv
-vsrc/ifu_ic_mem.sv
-vsrc/ifu_iccm_mem.sv
-vsrc/lsu_dccm_mem.sv
-vsrc/dmi_wrapper.sv
-vsrc/dmi_jtag_to_core_sync.sv
-vsrc/rvjtag_tap.sv
-vsrc/gated_latch.sv
-vsrc/beh_lib.sv
-vsrc/mem_lib.sv
+../design/src/main/resources/vsrc/mem.sv
+../design/src/main/resources/vsrc/ifu_ic_mem.sv
+../design/src/main/resources/vsrc/ifu_iccm_mem.sv
+../design/src/main/resources/vsrc/lsu_dccm_mem.sv
+../design/src/main/resources/vsrc/dmi_wrapper.sv
+../design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv
+../design/src/main/resources/vsrc/rvjtag_tap.sv
+../design/src/main/resources/vsrc/gated_latch.sv
+../design/src/main/resources/vsrc/beh_lib.sv
+../design/src/main/resources/vsrc/mem_lib.sv
 
 ./ahb_sif.sv
 ./axi_lsu_dma_bridge.sv

soc/soc_top.sv

@@ -1,19 +1,3 @@
-// SPDX-License-Identifier: Apache-2.0
-// Copyright 2020 Western Digital Corporation or its affiliates.
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-
 module soc_top (
     input  clk,
     input  dbg_rst,
@@ -24,6 +8,7 @@ module soc_top (
     input  jtag_tdi,
     input  jtag_trst_n
 );
+
   logic                       nmi_int;
 
   logic [               31:0] reset_vector;
@@ -104,6 +89,7 @@ module soc_top (
   logic [                4:0] wb_dest;
   logic [               31:0] wb_data;
 
+
   //-------------------------- LSU AXI signals--------------------------
   // AXI Write Channels
   wire                        lsu_axi_awvalid;
@@ -310,15 +296,15 @@ module soc_top (
     jtag_id[31:28] = 4'b1;
     jtag_id[27:12] = '0;
     jtag_id[11:1] = 11'h45;
-    reset_vector = 32'h0;
+    reset_vector = `RV_RESET_VEC;
     nmi_vector = 32'hee000000;
     nmi_int = 0;
-
-    $readmemh("program.hex", lmem.mem);
-    $readmemh("program.hex", imem.mem);
-
   end
 
+  //=========================================================================-
+  // RTL instance
+  //=========================================================================-
+  /* verilator lint_off PINMISSING */
   quasar_wrapper rvtop (
       .reset       (rst),
       .io_dbg_rst_l(dbg_rst),
@@ -812,6 +798,7 @@ module soc_top (
 
       .s0_wvalid(lmem_axi_wvalid),
       .s0_wready(lmem_axi_wready),
+
       .s0_bresp(lmem_axi_bresp),
       .s0_bvalid(lmem_axi_bvalid),
       .s0_bid(lmem_axi_bid),
@@ -836,8 +823,6 @@ module soc_top (
       .s1_bresp (dma_axi_bresp),
       .s1_bvalid(dma_axi_bvalid),
       .s1_bready(dma_axi_bready)
-
   );
 
-
 endmodule