Added layout_inference for UnidirectionalRnn
Added layout_inference so that can support tflite cases Modified copyright of code Modified case name and value name in UnidirectionalRnn unittest Type: Code Improvement Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
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@ -64,6 +64,7 @@
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#include "ops/transpose_layout_inference.h"
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#include "ops/unidirectional_lstm_layout_inference.h"
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#include "ops/broadcast_layout_inference.h"
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#include "ops/unidirectional_rnn_layout_inference.h"
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#include <algorithm>
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#include <deque>
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@ -267,6 +268,7 @@ std::vector<std::shared_ptr<vx::Tensor>> HandleLayoutInfer(
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_CONV3D, Conv3d);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_LSTM_OVXLIB, UnidirectionalLstm);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_EXPAND_BROADCAST, Broadcast);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_UNIDIRECTIONAL_SEQUENCE_RNN, UnidirectionalRnn);
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REGIST_LOGICAL_LAYOUT_INFERENCE(VSI_NN_OP_LOGICAL_OPS);
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REGIST_REDUCE_LAYOUT_INFERENCE(VSI_NN_OP_REDUCE);
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// use default layout inference
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@ -0,0 +1,99 @@
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/****************************************************************************
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*
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* Copyright (c) 2022 Vivante Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************/
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#ifndef TIM_LAYOUT_INFER_UNIDIRECTIONAL_RNN_LAYOUT_INFERENCE_H_
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#define TIM_LAYOUT_INFER_UNIDIRECTIONAL_RNN_LAYOUT_INFERENCE_H_
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#include "tim/vx/ops/reshape.h"
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#include "tim/vx/ops/nbg.h"
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#include "tim/vx/ops/transpose.h"
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#include "tim/vx/ops/batchnorm.h"
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#include "tim/vx/ops/clip.h"
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#include "ops/op_layout_inference.h"
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#include "permute_vector.h"
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#include "builtin_op_impl.h"
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namespace tim {
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namespace transform {
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class UnidirectionalRnnLayoutInfer : public OpLayoutInfer {
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public:
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UnidirectionalRnnLayoutInfer(
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const std::shared_ptr<vx::Operation> op,
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std::shared_ptr<layout_inference_impl::LayoutInferContext>& context)
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: OpLayoutInfer(op, context) {}
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// reverse any applied permute on it's input tensor
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void OnInputs(
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std::vector<std::shared_ptr<vx::Tensor>>& next_tensors) override {
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ReverseInputsPermuteVector();
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auto cloned_op = op_->Clone(context_->infer_graph_);
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for (const auto& i_src : op_->impl()->InputsTensor()) {
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std::shared_ptr<vx::Tensor> infer_tensor;
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std::shared_ptr<IPermuteVector> required_pv;
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if ((i_src->IsConstTensor() &&
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!(i_src->GetSpec().attr_ & vx::TensorAttribute::INPUT))) {
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infer_tensor = context_->infer_graph_->CreateTensor(
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i_src->GetSpec(), i_src->GetDataRef());
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context_->UpdateTensorMap(i_src, infer_tensor);
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}
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if (i_src->GetId() == (uint32_t)-1) {
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infer_tensor = context_->infer_graph_->CreateTensorPlaceHolder();
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context_->UpdateTensorMap(i_src, infer_tensor);
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}
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required_pv = MakeShared(i_src->GetShape().size());
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context_->SetPermuteVector(i_src, required_pv);
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}
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for (const auto& i_src : op_->impl()->InputsTensor()) {
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(*cloned_op).BindInput(context_->GetMapedTensor(i_src));
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}
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std::vector<std::shared_ptr<IPermuteVector>> required_pv_lst;
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for (auto out_tensor : op_->impl()->OutputsTensor()) {
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std::shared_ptr<vx::Tensor> infer_tensor;
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if (out_tensor->GetId() == (uint32_t)-1) {
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out_tensor = context_->infer_graph_->CreateTensorPlaceHolder();
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}
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required_pv_lst.push_back(MakeShared(out_tensor->GetShape().size()));
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}
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auto out_infer = CreateOutputsTensor(required_pv_lst);
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(*cloned_op).BindOutputs(out_infer);
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uint32_t i = 0;
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for (auto out_tensor : op_->impl()->OutputsTensor()) {
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context_->SetPermuteVector(out_tensor, required_pv_lst[i++]);
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next_tensors.push_back(out_tensor);
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}
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}
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};
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} // namespace transform
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} // namespace tim
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#endif
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@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2020 Vivante Corporation
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* Copyright (c) 2022 Vivante Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2021 Vivante Corporation
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* Copyright (c) 2022 Vivante Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -28,19 +28,19 @@
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#include "test_utils.h"
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#include "gtest/gtest.h"
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TEST(UnidirectionalSequenceRnn, shape_2_3_4_float_sigmoid) {
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TEST(UnidirectionalSequenceRnn, shape_2_3_2_float_sigmoid) {
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auto ctx = tim::vx::Context::Create();
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auto graph = ctx->CreateGraph();
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uint32_t input_size = 2, batch_size = 3, num_units = 4;
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uint32_t input_size = 2, batch_size = 3, num_units = 4, time_step = 2;
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tim::vx::ShapeType input_shape({input_size, batch_size, 2});
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tim::vx::ShapeType input_shape({input_size, batch_size, time_step});
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tim::vx::ShapeType weights_shape({input_size, num_units});
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tim::vx::ShapeType recurrent_weights_shape({num_units, num_units});
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tim::vx::ShapeType bias_shape({num_units});
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tim::vx::ShapeType recurrent_bias_shape({num_units});
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tim::vx::ShapeType state_in_shape({num_units, batch_size});
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tim::vx::ShapeType output_shape({num_units, batch_size, 2});
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tim::vx::ShapeType output_shape({num_units, batch_size, time_step});
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tim::vx::ShapeType state_out_shape({num_units, batch_size});
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tim::vx::TensorSpec input_spec(tim::vx::DataType::FLOAT32,
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@ -144,19 +144,19 @@ TEST(UnidirectionalSequenceRnn, shape_2_3_4_float_sigmoid) {
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}
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TEST(UnidirectionalSequenceRnn, shape_2_3_4_float_relu) {
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TEST(UnidirectionalSequenceRnn, shape_2_3_2_float_relu) {
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auto ctx = tim::vx::Context::Create();
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auto graph = ctx->CreateGraph();
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uint32_t input_size = 2, batch_size = 3, num_units = 4;
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uint32_t input_size = 2, batch_size = 3, num_units = 4, time_step = 2;
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tim::vx::ShapeType input_shape({input_size, batch_size, 2});
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tim::vx::ShapeType input_shape({input_size, batch_size, time_step});
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tim::vx::ShapeType weights_shape({input_size, num_units});
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tim::vx::ShapeType recurrent_weights_shape({num_units, num_units});
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tim::vx::ShapeType bias_shape({num_units});
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tim::vx::ShapeType recurrent_bias_shape({num_units});
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tim::vx::ShapeType state_in_shape({num_units, batch_size});
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tim::vx::ShapeType output_shape({num_units, batch_size, 2});
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tim::vx::ShapeType output_shape({num_units, batch_size, time_step});
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tim::vx::ShapeType state_out_shape({num_units, batch_size});
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tim::vx::TensorSpec input_spec(tim::vx::DataType::FLOAT32,
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